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    Method for forming a strained semiconductor structure
    11.
    发明授权
    Method for forming a strained semiconductor structure 有权
    形成应变半导体结构的方法

    公开(公告)号：US09299563B2

    公开(公告)日：2016-03-29

    申请号：US14313928

    申请日：2014-06-24

    Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

    Inventor： Seung Hun Lee ,  Liesbeth Witters ,  Roger Loo

    IPC: H01L21/02 ,  H01L21/762 ,  H01L29/10 ,  H01L21/3065

    CPC classification number: H01L21/02658 ,  H01L21/02587 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/1054

    Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.

    Abstract translation: 本发明涉及形成应变半导体结构的方法。 该方法包括提供应变松弛缓冲层，在应变松弛缓冲层上形成牺牲层，通过牺牲层形成浅沟槽隔离结构，去除牺牲层上的氧化物层的至少一部分，蚀刻通过牺牲层 使得应变松弛缓冲层的一部分被暴露，在应变松弛缓冲层的暴露部分上形成应变半导体结构。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20140061735A1

    公开(公告)日：2014-03-06

    申请号：US14015531

    申请日：2013-08-30

    Applicant: IMEC ,  Globalfoundries Inc. ,  Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Liesbeth Witters ,  Rita Vos ,  David Brunco ,  Marcus Johannes Henricus Van Dal

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

    Abstract: A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer.

    Abstract translation: 提供了一种用于制造晶体管器件的方法，所述晶体管器件包括基于锗的沟道层，所述方法包括在设置在衬底上的包含锗的沟道层上提供栅极结构，所述栅极结构设置在锗基源极区域和 在锗的相对侧的基于锗的漏极区域包括沟道层; 在锗基源和锗基漏极区上提供覆盖层，封盖层包含Si和Ge; 在覆盖层上沉积金属层; 进行温度步骤，从而将至少部分封盖层转变为不溶于适于溶解金属的预定蚀刻剂的金属锗硅化物; 通过预定的蚀刻剂从衬底中选择性地去除未消耗的金属; 并提供前金属介电层。

    METHODS FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE
    13.
    发明申请
    METHODS FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE 有权
    用于制造场效应半导体器件的方法

    公开(公告)号：US20140045315A1

    公开(公告)日：2014-02-13

    申请号：US13963932

    申请日：2013-08-09

    Applicant: IMEC

    Inventor： Liesbeth Witters

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7781 ,  H01L29/78684

    Abstract: A method of fabricating a field-effect transistor is disclosed. In one aspect, the method includes forming a channel layer comprising germanium over a substrate. The method additionally includes forming a gate structure on the channel layer, where the gate structure comprises a gate layer comprising silicon, and the gate layer has sidewalls above a surface of the channel layer. The method additionally includes forming sidewall spacers comprising silicon dioxide on the sidewalls by subjecting the gate structure to a solution adapted for forming a chemical silicon oxide on materials comprising silicon. The method further includes forming elevated source/drain structures on the channel layer adjacent to the gate structure by selectively epitaxially growing a source/drain material on the channel layer.

    Abstract translation: 公开了一种制造场效晶体管的方法。 在一个方面，该方法包括在衬底上形成包含锗的沟道层。 该方法还包括在沟道层上形成栅极结构，其中栅极结构包括包含硅的栅极层，并且栅极层在沟道层的表面上方具有侧壁。 该方法还包括在侧壁上形成包含二氧化硅的侧壁间隔物，该栅极结构适于在包含硅的材料上形成化学氧化硅。 该方法还包括通过在沟道层上选择性地外延生长源极/漏极材料，在与栅极结构相邻的沟道层上形成升高的源极/漏极结构。

    Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof
    14.
    发明申请
    Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof 有权
    包含硅和锗的互补金属氧化物半导体器件及其制造方法

    公开(公告)号：US20140008730A1

    公开(公告)日：2014-01-09

    申请号：US13935324

    申请日：2013-07-03

    Applicant: IMEC

    Inventor： Jerome Mitard ,  Liesbeth Witters

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

    Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

    Abstract translation: 公开了互补金属氧化物半导体（CMOS）器件和制造这种CMOS器件的方法。 在一些实施例中，示例CMOS器件可以包括衬底和形成在衬底上的缓冲层，其中缓冲层包括Si1-xGex，其中x小于0.5。 示例CMOS器件还可以包括一个或多个pMOS沟道层元件，其中每个pMOS沟道层元件包括Si1-yGey，并且其中y大于x。 示例CMOS器件还可以包括一个或多个nMOS沟道层元件，其中每个nMOS沟道层元件包括Si1-zGez，并且其中z小于x。 在一些实施例中，示例CMOS器件可以是鳍状场效应晶体管（FinFET）CMOS器件，并且还可以包括包括pMOS沟道层元件的第一鳍结构和包括nMOS沟道层元件的第二鳍结构 s）。

    LOW PARASITIC Ccb HETEROJUNCTION BIPOLAR TRANSISTOR
    16.
    发明申请
    LOW PARASITIC Ccb HETEROJUNCTION BIPOLAR TRANSISTOR 有权

    公开(公告)号：US20210167187A1

    公开(公告)日：2021-06-03

    申请号：US17103031

    申请日：2020-11-24

    Applicant: IMEC VZW

    Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

    IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

    Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

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