公开(公告)号：US20170083469A1

公开(公告)日：2017-03-23

申请号：US15250067

申请日：2016-08-29

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Praveen Raghavan

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F15/17362 ,  G06F15/7807

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P

公开(公告)号：US10147637B2

公开(公告)日：2018-12-04

申请号：US15889043

申请日：2018-02-05

Applicant: IMEC VZW

Inventor： Youssef Drissi ,  Ryan Ryoung han Kim ,  Stephane Lariviere ,  Praveen Raghavan ,  Darko Trivkovic

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.

公开(公告)号：US10127961B2

公开(公告)日：2018-11-13

申请号：US15367293

申请日：2016-12-02

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Raf Appeltans ,  Praveen Raghavan

IPC: G11C11/00 ,  G11C11/16

Abstract: Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells provided. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.

公开(公告)号：US10073802B2

公开(公告)日：2018-09-11

申请号：US15250067

申请日：2016-08-29

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Praveen Raghavan

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F15/17362 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P

公开(公告)号：US20180248111A1

公开(公告)日：2018-08-30

申请号：US15904189

申请日：2018-02-23

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Praveen Raghavan ,  Davide Francesco Crotti ,  Raf Appeltans

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  G11C5/06

Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer. The device additionally includes a magnetic tunnel junction (MTJ) device including a bottom layer, a top layer and an MTJ structure arranged between the bottom layer and the top layer, wherein the bottom layer is connected to a bottom layer contact portion of the first set of conductive paths and the top layer is connected to a top layer contact portion of the second or third set of conductive paths. The device further includes a multi-level via extending through the second dielectric layer and the third dielectric layer, between a first via contact portion of the first set of conductive paths and a second via contact portion of the third set of conductive paths, wherein a height of the MTJ device corresponds to, or is less than, a height of the multi-level via.

公开(公告)号：US10043798B2

公开(公告)日：2018-08-07

申请号：US15247127

申请日：2016-08-25

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Praveen Raghavan ,  Steven Demuynck ,  Julien Ryckaert

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L21/74 ,  H01L29/78

Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

公开(公告)号：US20180174642A1

公开(公告)日：2018-06-21

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/408 ,  H01L29/08 ,  H01L29/423

CPC classification number: G11C11/412 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

公开(公告)号：US20170169873A1

公开(公告)日：2017-06-15

申请号：US15367293

申请日：2016-12-02

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Raf Appeltans ,  Praveen Raghavan

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

CPC classification number: G11C11/1675 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673

Abstract: Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells are disclosed. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.

公开(公告)号：US20150162448A1

公开(公告)日：2015-06-11

申请号：US14565159

申请日：2014-12-09

Applicant: IMEC VZW

Inventor： Praveen Raghavan ,  Jan Genoe ,  Soeren Steudel

IPC: H01L29/786 ,  H01L29/66 ,  H03K17/687 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L23/525 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

Abstract: The disclosed technology generally relates to integrated circuit (IC), and more particularly to IC devices having one or more power gating switches and methods of fabricating the same. In one aspect, an IC device comprises a front end-of-the-line (FEOL) portion and a back end-of-the-line (BEOL) portion electrically connected to the FEOL portion. The BEOL portion comprises a plurality of metallization levels, wherein each metallization level comprises a plurality of metal lines extending in a lateral direction and a plurality of conductive vertical via structures. The IC device further comprises a power gating transistor formed in the BEOL portion and in direct electrical contact with at least one of the via structures or one of the metal lines.

Abstract translation: 所公开的技术通常涉及集成电路（IC），更具体地涉及具有一个或多个电源门控开关的IC器件及其制造方法。 一方面，IC器件包括电连接到FEOL部分的前端（FEOL）部分和后端（BEOL）部分。 BEOL部分包括多个金属化水平，其中每个金属化水平包括沿横向方向延伸的多个金属线和多个导电垂直通孔结构。 IC器件还包括形成在BEOL部分中并与至少一个通孔结构或金属线之一直接电接触的电源门控晶体管。

公开(公告)号：US11475101B2

公开(公告)日：2022-10-18

申请号：US16685892

申请日：2019-11-15

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Dimitrios Rodopoulos ,  Mohit Dandekar

IPC: G06F17/15 ,  G06N3/04 ,  G06N3/08

Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.