公开(公告)号：US09706656B2

公开(公告)日：2017-07-11

申请号：US14950584

申请日：2015-11-24

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Jing-Yao Chang ,  Tao-Chih Chang ,  Ren-Shin Cheng ,  Min-Lin Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0251 ,  H05K3/42 ,  H05K2201/0187 ,  H05K2201/09545 ,  H05K2203/1105 ,  H05K2203/1178 ,  H05K2203/143 ,  H05K2203/1438

Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

公开(公告)号：US09343393B2

公开(公告)日：2016-05-17

申请号：US14570684

申请日：2014-12-15

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Peng-Shu Chen ,  Shih-Hsien Wu

IPC: H01L23/48 ,  H01L23/64 ,  H01L23/522 ,  H01L21/02 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L23/14

CPC classification number: H01L23/481 ,  H01L21/02107 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/64 ,  H01L23/66 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/81192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3011

Abstract: A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on the first surface of the semiconductor material layer. The second isolation layer is located on the second surface of the semiconductor material layer. The first conductive pillar, supplied with a first voltage, penetrates the semiconductor material layer, the first isolation layer, and the second isolation layer. The second conductive pillar is supplied with to a second voltage, and a part of the second conductive pillar is formed in the second isolation layer, the second conductive pillar penetrates the second isolation layer and touches the second surface of the semiconductor material layer.

Abstract translation: 半导体衬底组件包括半导体材料层，第一隔离层，第二隔离层，第一导电柱和第二导电柱。 半导体材料层具有与第一表面相对的第一表面和第二表面。 第一隔离层位于半导体材料层的第一表面上。 第二隔离层位于半导体材料层的第二表面上。 提供有第一电压的第一导电柱穿透半导体材料层，第一隔离层和第二隔离层。 第二导电柱被提供到第二电压，并且第二导电柱的一部分形成在第二隔离层中，第二导电柱穿透第二隔离层并接触半导体材料层的第二表面。

公开(公告)号：US09258883B2

公开(公告)日：2016-02-09

申请号：US14809607

申请日：2015-07-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Shih-Hsien Wu ,  Min-Lin Lee

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0227 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4685 ,  H05K2201/09854 ,  Y10T29/49165

Abstract: A via structure includes a ground conductor, a floated conductor and a signal conductor. The ground conductor is electrically coupled to a reference potential. The floated conductor is electrically insulated from the ground conductor. The signal conductor is located between and insulated from the ground conductor and the floated conductor.

Abstract translation: 通孔结构包括接地导体，浮动导体和信号导体。 接地导体电耦合到参考电位。 浮动导体与接地导体电绝缘。 信号导体位于接地导体和浮动导体之间并与之绝缘。

公开(公告)号：US11469484B2

公开(公告)日：2022-10-11

申请号：US16821283

申请日：2020-03-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Hsiang En Ding ,  Shih-Hsien Wu

IPC: H01P3/08 ,  H01P11/00

Abstract: A circuit structure includes a substrate integrated waveguide, a substrate disposed on the substrate integrated waveguide, a waveguide signal feeding element and a ring-shaped conductive element. The substrate integrated waveguide includes another substrate having a waveguide transmitting region, two conductive layers disposed on this substrate and covering the waveguide transmitting region, and at least one waveguide conductive element passing through this substrate and electrically connected to the two conductive layers. The at least one waveguide conductive element surrounds the waveguide transmitting region. One of the conductive layers is located between the two substrates. The waveguide signal feeding element passes through one substrate and one conductive layer between the substrates, and the waveguide signal feeding element extends to the waveguide transmitting region. The waveguide signal feeding element is electrically insulated from one conductive layer. The ring-shaped conductive element is disposed in one substrate and surrounds the waveguide signal feeding element.

公开(公告)号：US20220201870A1

公开(公告)日：2022-06-23

申请号：US17126033

申请日：2020-12-18

Applicant: Industrial Technology Research Institute

Inventor： Chien-Min Hsu ,  Chih-Ming Shen ,  Shih-Hsien Wu

IPC: H05K3/30 ,  H05K1/18

Abstract: A fabrication method of a flexible electronic package device including the following steps is provided. A tolerable bending radius of the flexible electronic package device is obtained. A minimum surface curvature radius of a selected portion of an applied carrier is obtained. A relationship of the tolerable bending radius being smaller than the minimum surface curvature radius is ensured. The flexible electronic package device is disposed on the selected portion.

公开(公告)号：US11363724B1

公开(公告)日：2022-06-14

申请号：US17126033

申请日：2020-12-18

Applicant: Industrial Technology Research Institute

Inventor： Chien-Min Hsu ,  Chih-Ming Shen ,  Shih-Hsien Wu

IPC: H05K3/30 ,  H05K1/18 ,  H01L23/498 ,  H01L23/00

Abstract: A fabrication method of a flexible electronic package device including the following steps is provided. A tolerable bending radius of the flexible electronic package device is obtained. A minimum surface curvature radius of a selected portion of an applied carrier is obtained. A relationship of the tolerable bending radius being smaller than the minimum surface curvature radius is ensured. The flexible electronic package device is disposed on the selected portion.

公开(公告)号：US09125304B2

公开(公告)日：2015-09-01

申请号：US14226526

申请日：2014-03-26

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Shih-Hsien Wu ,  Min-Lin Lee

IPC: H05K1/11 ,  H05K3/10 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0227 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4685 ,  H05K2201/09854 ,  Y10T29/49165

Abstract: The disclosure provides a manufacturing method for a circuit board having a via and including a substrate, a ground conductor, a floated conductor and a signal conductor. The substrate includes a second sheet layer, a second ground layer, a core layer, a first ground layer and a first sheet layer that are stacked in sequence from bottom to top. The ground conductor penetrates through the core layer and is electrically coupled to the first ground layer and the second ground layer. The floated conductor penetrates through the core layer and is electrically insulated from the first ground layer, the second ground layer and the ground conductor. The signal conductor penetrates through the substrate, being located between the ground conductor and the floated conductor, and insulated from the first ground layer, the second ground layer, the ground conductor and the floated conductor.

Abstract translation: 本发明提供了一种具有通孔并且包括衬底，接地导体，浮动导体和信号导体的电路板的制造方法。 基板包括从底部到顶部依次层叠的第二片层，第二接地层，芯层，第一接地层和第一片层。 接地导体穿过芯层并电耦合到第一接地层和第二接地层。 浮动导体穿过芯层，并与第一接地层，第二接地层和接地导体电绝缘。 信号导体穿过衬底，位于接地导体和浮动导体之间，并与第一接地层，第二接地层，接地导体和浮动导体绝缘。

公开(公告)号：US09029984B2

公开(公告)日：2015-05-12

申请号：US13797366

申请日：2013-03-12

Applicant: Industrial Technology Research Institute

Inventor： Peng-Shu Chen ,  Min-Lin Lee ,  Shih-Hsien Wu ,  Shur-Fen Liu

IPC: H01L29/00 ,  H01L23/48 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L23/498 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L23/48 ,  H01L21/02107 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/64 ,  H01L23/66 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad.

Abstract translation: 提出了一种半导体衬底组件。 半导体插入器包括具有第一表面和与第一表面相对的第二表面的衬底，第一导电焊盘，第二导电焊盘和导电柱。 第一导电焊盘形成在基板的第一表面的预定位置处。 与第一导电焊盘的位置相比，第二导电焊盘形成在基板的第二表面的预定位置处。 导电柱形成在基板中并与第一导电焊盘和第二导电焊盘之一接触。

公开(公告)号：US20140177189A1

公开(公告)日：2014-06-26

申请号：US13912207

申请日：2013-06-07

Applicant: Industrial Technology Research Institute

Inventor： Chang-Chih Liu ,  Hsun Yu ,  Peng-Shu Chen ,  Shih-Hsien Wu

IPC: H05K1/14

CPC classification number: H01L25/00 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17106 ,  H01L2224/17515 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

Abstract translation: 提供了包括多个微型块结构，多个第一基板，至少一个第一空间层，多个第二基板和至少一个第二空间层的芯片堆叠结构。 第一基板通过微型块结构的一部分彼此堆叠，并且每个第一基板包括至少一个第一再分布层。 第一空间层位于堆叠的第一基板之间。 第二基板通过微型块结构的另一部分堆叠在至少一个第一基板上，并且每个第二基板包括至少一个第二再分布层。 第二空间层位于堆叠的第一和第二基板之间。 第一再分布层，第二再分配层和微型块结构形成多个阻抗元件，并且阻抗元件提供特定的振荡频率。