公开(公告)号：US20150332938A1

公开(公告)日：2015-11-19

申请号：US14279752

申请日：2014-05-16

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Edward Fuergut ,  Irmgard Escher-Poeppel

IPC: H01L21/56 ,  H01L25/065 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68318 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A method of manufacturing an electronic device package includes structuring a metal layer to generate a structured metal layer having a plurality of openings. Semiconductor chips are placed into at least some of the openings. An encapsulating material is applied over the structured metal layer and the semiconductor chips to form an encapsulation body. The encapsulation body is separated into a plurality of electronic device packages.

Abstract translation: 制造电子器件封装的方法包括构造金属层以产生具有多个开口的结构化金属层。 将半导体芯片放置在至少一些开口中。 在结构化金属层和半导体芯片上施加封装材料以形成封装体。 封装体被分离成多个电子器件封装。

公开(公告)号：US20200227312A1

公开(公告)日：2020-07-16

申请号：US16690984

申请日：2019-11-21

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Thorsten Scharf ,  Catharina Wille

IPC: H01L21/768 ,  H01L23/16 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor device and method is disclosed. In one example, the method includes forming a recess in an electrically insulating encapsulation material, wherein the encapsulation material at least partly encapsulates a semiconductor chip. The method further includes forming an adhesion promoting structure in the recess. The method further includes spraying an electrically conductive material into the recess, wherein the adhesion promoting structure is configured to provide an adhesion between the sprayed electrically conductive material and the encapsulation material.

公开(公告)号：US20200006187A1

公开(公告)日：2020-01-02

申请号：US16452777

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Scharf

IPC: H01L23/367 ,  H01L23/495 ,  H01L23/532 ,  H01L23/373 ,  H01L23/31

Abstract: A heat dissipation device includes a first part having a first material and a surface portion, and a second part on the surface portion. The second part has a second material and a porosity.

公开(公告)号：US20190304858A1

公开(公告)日：2019-10-03

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/40 ,  H01L23/00 ,  H01L23/08

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US09620459B2

公开(公告)日：2017-04-11

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00 ,  H01L23/051 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/90 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/33181 ,  H01L2224/82039 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/35 ,  H01L2924/00

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

公开(公告)号：US10886186B2

公开(公告)日：2021-01-05

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/08 ,  H01L23/00 ,  H01L23/40

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US10573533B2

公开(公告)日：2020-02-25

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L23/31 ,  H01L21/268 ,  H01L21/04 ,  H01L21/225 ,  H01L21/285

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US20190013210A1

公开(公告)日：2019-01-10

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L21/285 ,  H01L21/225 ,  H01L21/04 ,  H01L21/321 ,  H01L21/268 ,  H01L23/31

CPC classification number: H01L21/324 ,  H01L21/0455 ,  H01L21/0485 ,  H01L21/2254 ,  H01L21/2258 ,  H01L21/268 ,  H01L21/28512 ,  H01L21/28575 ,  H01L23/3157

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US10014275B2

公开(公告)日：2018-07-03

申请号：US15459151

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Andreas Munding ,  Catharina Wille

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/16 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/095 ,  H01L2224/16104 ,  H01L2224/16112 ,  H01L2224/16137 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.