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    Devices and methods for data storage
    11.
    发明授权
    Devices and methods for data storage 有权

    公开(公告)号：US11327835B2

    公开(公告)日：2022-05-10

    申请号：US16944697

    申请日：2020-07-31

    Applicant: Infineon Technologies AG

    Inventor： Georg Georgakos ,  Michael Goessel

    IPC: G06F11/10 ,  G11C29/52

    Abstract: In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.

    Compensation of read errors
    12.
    发明授权
    Compensation of read errors 有权

    公开(公告)号：US11157352B2

    公开(公告)日：2021-10-26

    申请号：US16575598

    申请日：2019-09-19

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel

    IPC: G06F11/10 ,  G11C7/10 ,  G11C29/52 ,  G11C13/00 ,  G11C11/16 ,  G06F3/06 ,  G06F11/07

    Abstract: A method for compensating for a read error is disclosed, wherein each of n states are read from memory cells of a memory, the states being determined in a time domain. If the n states do not form a code word of a k-from-n code, a plurality of states from the n states, which were determined within a reading window, are provided with a first valid assignment and fed to an error processing stage. If the error processing does not indicate an error, the n states are further processed with the first valid assignment, and if the error processing indicates an error, the plurality of states that were determined within the reading window are provided with a second valid assignment and the n states are further processed with the second valid assignment. Accordingly, a device, a system and a computer program product are also disclosed.

    DETECTION OF CODEWORDS
    13.
    发明申请
    DETECTION OF CODEWORDS 审中-公开

    公开(公告)号：US20200350931A1

    公开(公告)日：2020-11-05

    申请号：US16716735

    申请日：2019-12-17

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel

    IPC: H03M13/39 ,  H03M13/25 ,  H03M13/00

    Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

    MEMORY HAVING DIFFERENT RELIABILITIES
    14.
    发明申请
    MEMORY HAVING DIFFERENT RELIABILITIES 审中-公开

    公开(公告)号：US20200089418A1

    公开(公告)日：2020-03-19

    申请号：US16690384

    申请日：2019-11-21

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Albrecht Mayer

    IPC: G06F3/06 ,  G11C11/56 ,  G06F11/10 ,  G06F11/07

    Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

    Memory device and method for correcting a stored bit sequence
    15.
    发明授权
    Memory device and method for correcting a stored bit sequence 有权

    公开(公告)号：US10109372B2

    公开(公告)日：2018-10-23

    申请号：US15235741

    申请日：2016-08-12

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

    IPC: G11C29/00 ,  G11C29/52 ,  G11C29/42 ,  G11C11/16 ,  G11C29/04

    Abstract: A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (x1/T) assigned to the first memory cells. The frequency (x1/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.

    Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories
    16.
    发明授权
    Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories 有权

    公开(公告)号：US09646716B2

    公开(公告)日：2017-05-09

    申请号：US14447806

    申请日：2014-07-31

    Applicant: Infineon Technologies AG

    Inventor： Michael Goessel ,  Sven Hosp ,  Guenther Niess ,  Klaus Oberlaender

    IPC: H03M13/11 ,  G11C29/10 ,  G06F11/263 ,  G11C29/42 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G11C29/10 ,  G06F11/1048 ,  G06F11/263 ,  G11C29/42 ,  G11C2029/0411

    Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).

    MEMORY DEVICE AND METHOD FOR CORRECTING A STORED BIT SEQUENCE
    17.
    发明申请
    MEMORY DEVICE AND METHOD FOR CORRECTING A STORED BIT SEQUENCE 审中-公开
    存储器件和校正存储器位序列的方法

    公开(公告)号：US20170046223A1

    公开(公告)日：2017-02-16

    申请号：US15235741

    申请日：2016-08-12

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    CPC classification number: G11C29/52 ,  G11C11/1677 ,  G11C29/42 ,  G11C2029/0409

    Abstract: A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (×1/T) assigned to the first memory cells. The frequency (×1/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.

    Abstract translation: 存储器装置包括具有与第一存储器单元不同的第一存储单元和第二存储单元的存储器。 在第一存储器单元中存储第一位序列，并且在第二存储器单元中存储第二位序列。 存储装置包括存储器控制器，其被配置为以分配给第一存储器单元的频率（×1 / T）来检查第一位序列。 分配给第一存储器单元的频率（×1 / T）取决于第一存储器单元的可靠性信息项。 在存在错误状态的情况下，存储器控制器被配置以校正第一位序列的错误位并且将至少校正的位回写到存储器中。 基于第二存储器单元的可靠性信息项，比第一比特序列更频繁地检查第二比特序列。

    Circuitry and Method for Multi-Bit Correction
    19.
    发明申请
    Circuitry and Method for Multi-Bit Correction 有权
    多位校正的电路和方法

    公开(公告)号：US20140122967A1

    公开(公告)日：2014-05-01

    申请号：US13664495

    申请日：2012-10-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Thomas Kern ,  Michael Goessel

    IPC: G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006

    Abstract: A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.

    Abstract translation: 提供了一种电路，其包括包括多个存储器单元的存储器，其中存储器的多个存储器单元中的至少一个被配置为采取至少三种不同状态中的一种。 电路还包括第一子电路BT，其被配置为基于二进制值的序列产生多个三进制输出值，第二子电路LH被配置为基于一个或多个状态将一个或多个三态状态值转换为二进制辅助读取值 值和被配置为生成一个或多个二进制校验位的编码器，其中所述编码器被配置为将所生成的一个或多个校验位中的每一个存储在不同的存储器单元中。

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