公开(公告)号：US20250112077A1

公开(公告)日：2025-04-03

申请号：US18478391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Andrey Vyatskikh ,  Adel Elsherbini ,  Brandon M. Rawlings ,  Tushar Kanti Talukdar ,  Thomas L. Sounart ,  Kimin Jun ,  Johanna Swan ,  Grant M. Kloster ,  Carlos Bedoya Arroyave

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/538

Abstract: An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.

公开(公告)号：US11749628B2

公开(公告)日：2023-09-05

申请号：US18053869

申请日：2022-11-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Veronica Aleman Strong ,  Shawna M. Lift ,  Brandon M. Rawlings ,  Jagat Shakya ,  Johanna M. Swan ,  David M. Craig ,  Jeremy Alan Streifer ,  Brennen Karl Mueller

IPC: H01L23/00 ,  H01L21/18 ,  B81B7/00

CPC classification number: H01L24/06 ,  B81B7/0006 ,  B81B7/007

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

公开(公告)号：US20230187362A1

公开(公告)日：2023-06-15

申请号：US17548078

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Brandon M. Rawlings ,  Shawna M. Liff ,  Bradley A. Jackson ,  Robert J. Munoz ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L25/0652 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/96

Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

公开(公告)号：US20230074970A1

公开(公告)日：2023-03-09

申请号：US18053869

申请日：2022-11-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Veronica Aleman Strong ,  Shawna M. Liff ,  Brandon M. Rawlings ,  Jagat Shakya ,  Johanna M. Swan ,  David M. Craig ,  Jeremy Alan Streifer ,  Brennen Karl Mueller

IPC: H01L23/00 ,  B81B7/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

公开(公告)号：US10381291B2

公开(公告)日：2019-08-13

申请号：US15745701

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Brandon M. Rawlings ,  Aleksandar Aleksov ,  Feras Eid ,  Javier Soto

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.

公开(公告)号：US09713264B2

公开(公告)日：2017-07-18

申请号：US14576107

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Henning Braunisch

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K3/0082 ,  H05K1/116 ,  H05K3/422 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4679 ,  H05K2201/09463 ,  H05K2201/09854 ,  H05K2203/0505

Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

公开(公告)号：US20250112196A1

公开(公告)日：2025-04-03

申请号：US18478843

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Adel Elsherbini ,  Thomas L. Sounart ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Kimin Jun ,  Andrey Vyatskikh ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/373 ,  H01L23/38 ,  H01L23/433 ,  H01L23/538 ,  H10N19/00

Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.

公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US11227825B2

公开(公告)日：2022-01-18

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/03 ,  H05K1/16 ,  H01F17/00 ,  H01F17/06 ,  H01L21/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/60 ,  G11B5/17 ,  G11B5/31 ,  G11B5/147 ,  G11B5/187 ,  H01L23/498 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.