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    METHODS AND APPARATUS TO IMPROVE FLIP-FLOP TOGGLE EFFICIENCY
    14.
    发明公开
    METHODS AND APPARATUS TO IMPROVE FLIP-FLOP TOGGLE EFFICIENCY 审中-公开

    公开(公告)号：US20240333263A1

    公开(公告)日：2024-10-03

    申请号：US18191562

    申请日：2023-03-28

    Applicant: Intel Corporation

    Inventor： Chinmay Pradeep Joshi ,  Dinesh Somasekhar ,  David Edward Bradley ,  Radhika Kudva

    IPC: H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/012 ,  H03K3/0372

    Abstract: Methods and apparatus are disclosed to improve flip-flop toggle efficiency. An example circuit includes an upper flip-flop latch circuit including a first clock input terminal, a first output terminal, and a first data input terminal, a first gating circuit including a first gating transistor, the first gating transistor including a first power input terminal, a first gating output terminal and a gating signal input terminal, the gating signal input terminal coupled to the first input terminal of the first flip-flop latch circuit, a first clock transistor including a clock power input terminal coupled to the first gating output terminal of the first gating transistor, a clock power output terminal, and a clock signal input terminal coupled to the first clock input terminal of the upper flip-flop latch circuit, and a first latch output transistor including a latch power input terminal, a latch power output terminal coupled to the clock power output terminal of the first clock transistor, and a latch input terminal coupled to an output of a second latch output transistor of the upper flip-flop latch circuit.

    Innovative way to design silicon to overcome reticle limit
    15.
    发明授权
    Innovative way to design silicon to overcome reticle limit 有权

    公开(公告)号：US11476185B2

    公开(公告)日：2022-10-18

    申请号：US16481421

    申请日：2017-04-01

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Dinesh Somasekhar ,  Dheeraj Subbareddy

    IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/07

    Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.

    Multi-bit read-only memory device
    16.
    发明授权
    Multi-bit read-only memory device 有权

    公开(公告)号：US11152060B2

    公开(公告)日：2021-10-19

    申请号：US16449285

    申请日：2019-06-21

    Applicant: Intel Corporation

    Inventor： Xiaofei Wang ,  Dinesh Somasekhar ,  Clifford Ong ,  Eric A Karl ,  Zheng Guo ,  Gordon Carskadon

    IPC: G11C11/56 ,  G11C17/12 ,  H01L27/112

    Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

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