公开(公告)号：US08994344B2

公开(公告)日：2015-03-31

申请号：US13727227

申请日：2012-12-26

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  Peter Hazucha ,  Jaeseo Lee ,  Tanay Karnik ,  Vivek K. De ,  Fabrice Paillet

IPC: G05F1/46 ,  H02M1/14 ,  H02M7/06

CPC classification number: G05F1/468 ,  H02M1/14 ,  H02M7/068

Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.

公开(公告)号：US11747371B2

公开(公告)日：2023-09-05

申请号：US17006715

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim ,  Fabrice Paillet

IPC: G01R19/00 ,  H03F1/34 ,  H03F3/45 ,  H02M3/158 ,  G01R1/30 ,  H03F1/42 ,  G05F3/26 ,  H02M1/00

CPC classification number: G01R19/0023 ,  G01R1/30 ,  G05F3/262 ,  H02M3/158 ,  H03F1/34 ,  H03F1/42 ,  H03F3/45748 ,  H02M1/0009 ,  H03F2203/45084

Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.

公开(公告)号：US11658570B2

公开(公告)日：2023-05-23

申请号：US17009661

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Harish Krishnamurthy ,  Sheldon Weng ,  Nachiket Desai ,  Suhwan Kim ,  Fabrice Paillet

IPC: G06F1/00 ,  H02M3/157 ,  G06F1/26 ,  H02M3/158 ,  H03H17/02

CPC classification number: H02M3/157 ,  G06F1/26 ,  H02M3/1584 ,  H03H17/0211

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

公开(公告)号：US20210075316A1

公开(公告)日：2021-03-11

申请号：US16563495

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Takao Oshita ,  Fabrice Paillet ,  Rinkle Jain ,  Jad Rizk ,  Danny Bronstein ,  Ahmad Arnaot

IPC: H02M3/07 ,  H02M1/00 ,  H03K5/24 ,  G06F1/3234

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

公开(公告)号：US09696350B2

公开(公告)日：2017-07-04

申请号：US13907802

申请日：2013-05-31

Applicant: INTEL CORPORATION

Inventor： Edward A. Burton ,  Gerhard Schrom ,  Michael W. Rogers ,  Alexander Lyakhov ,  Ravi Sankar Vunnam ,  Jonathan P. Douglas ,  Fabrice Paillet ,  J. Keith Hodgson ,  William Dawson Kesling ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan ,  Samie Samaan ,  George Geannopoulos

IPC: H02M3/157 ,  G01R19/00 ,  H03L5/00 ,  H03M1/66 ,  G06T3/40 ,  H02M3/156 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

CPC classification number: G01R19/0092 ,  G06T3/40 ,  H02M1/088 ,  H02M3/156 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0009 ,  H02M2003/1566 ,  H03L5/00 ,  H03M1/66 ,  H03M1/685

Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

公开(公告)号：US20220239222A1

公开(公告)日：2022-07-28

申请号：US17714969

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Takao Oshita ,  Fabrice Paillet ,  Rinkle Jain ,  Jad Rizk ,  Danny Bronstein ,  Ahmad Arnaot

IPC: H02M3/07 ,  H02M1/00 ,  G06F1/3234 ,  H03K5/24

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

公开(公告)号：US11204766B2

公开(公告)日：2021-12-21

申请号：US16557187

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Jason Seung-Min Kim ,  Nitin N. Garegrat ,  Anitha Loke ,  Nasima Parveen ,  David Y. Fang ,  Kursad Kiziloglu ,  Dmitry Sergeyevich Lukiyanchenko ,  Fabrice Paillet ,  Andrew Yang

IPC: G06F9/30

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

公开(公告)号：US10367409B2

公开(公告)日：2019-07-30

申请号：US15402021

申请日：2017-01-09

Applicant: INTEL CORPORATION

Inventor： Gerhard Schrom ,  Narayanan Raghuraman ,  Fabrice Paillet

IPC: H02M1/14 ,  H03K4/06 ,  G06F1/26 ,  H03L7/00 ,  H03K3/03 ,  H03K7/08 ,  H03K5/134 ,  H02M3/158 ,  H03H7/32 ,  H03H11/26 ,  H03K5/133 ,  H03K5/00

Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.