公开(公告)号：US20220068821A1

公开(公告)日：2022-03-03

申请号：US17090919

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/552 ,  H01L21/48

Abstract: A device is provided, including a package substrate, a first interposer including a plurality of first vias extending through the first interposer, and a second interposer including a plurality of second vias extending through the second interposer. The first interposer and the second interposer may be arranged on the package substrate and may be spaced apart from each other.

公开(公告)号：US20210384130A1

公开(公告)日：2021-12-09

申请号：US16987405

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Yang Liang POH ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

公开(公告)号：US20180294252A1

公开(公告)日：2018-10-11

申请号：US15766150

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Ping Ping OOI ,  Kooi Chi OOI ,  Shanggar PERIAMAN

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：US20170170676A1

公开(公告)日：2017-06-15

申请号：US14964466

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Kooi Chi OOI ,  Mark A. SCHAECHER ,  Teong Guan YEW ,  Eng Huat GOH

IPC: H02J7/02 ,  H02J50/10 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H02J7/025 ,  H01F27/36 ,  H01F38/14 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L25/50 ,  H02J50/10

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

公开(公告)号：US20240006786A1

公开(公告)日：2024-01-04

申请号：US17857051

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Howe Yin LOO ,  Tin Poay CHUAH ,  Jenny Shio Yin ONG ,  Chee Min LOH ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM ,  Kooi Chi OOI

IPC: H01R12/57 ,  H01R12/70

CPC classification number: H01R12/57 ,  H01R12/7082 ,  H01R12/707

Abstract: The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface. In an aspect, the second-type of printed circuit board is configured to be embedded in the first-type of printed circuit board and the first-type of printed circuit board is configured to receive the second-type of printed circuit board.

公开(公告)号：US20240006324A1

公开(公告)日：2024-01-04

申请号：US17857057

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/5386 ,  H01L2924/1436 ,  H01L2924/1432 ,  H01L2924/1421 ,  H01L2924/3511 ,  H01L2924/30101 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface. The semiconductor package further includes a second device including a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface, and a bridge including a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.

公开(公告)号：US20230163101A1

公开(公告)日：2023-05-25

申请号：US17535606

申请日：2021-11-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Chia Chuan WU ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L25/065 ,  H01L27/108 ,  G11C5/06 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L27/10805 ,  G11C5/06 ,  H01L23/5384 ,  H01L27/10847 ,  H01L21/76802

Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a package substrate, an interposer with a redistribution layer positioned on the interposer. A recess may be formed in a bottom surface in the interposer and a plurality of through silicon vias may be formed in the interposer, including the recess, that are coupled to a bottom surface of the redistribution layer. A recess device may be positioned in the recess and coupled to the redistribution layer. A top-side device may be positioned on and coupled to a top surface of the redistribution layer, and a footprint of the top-side device may be aligned to overlap the recess device. In an aspect, the recess device and the top-side device may be stacked memory devices, e.g., DRAMs, SRAMs, and/or other memory devices.

公开(公告)号：US20220068782A1

公开(公告)日：2022-03-03

申请号：US17089749

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/13

Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.

公开(公告)号：US20210335718A1

公开(公告)日：2021-10-28

申请号：US17368837

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.

公开(公告)号：US20210335698A1

公开(公告)日：2021-10-28

申请号：US17367684

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Chia Chuan WU ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/367 ,  H01L25/065 ,  H01L21/48

Abstract: According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.