-
公开(公告)号：US20190103411A1
公开(公告)日：2019-04-04
申请号：US15721771
申请日：2017-09-30
Applicant: Intel Corporation
Inventor： Haitao Liu , Guangyu Huang , Krishna K. Parat , Shrotri B. Kunal , Srikant Jayanti
IPC: H01L27/11524 , H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L29/51
Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.
-
公开(公告)号：US20150333085A1
公开(公告)日：2015-11-19
申请号：US14813398
申请日：2015-07-30
Applicant: Intel Corporation
Inventor： Haitao Liu , Chandra V. Mouli , Krishna K. Parat , Jie Sun , Guangyu Huang
IPC: H01L27/115 , H01L29/04 , G11C16/06 , H01L29/16
CPC classification number: H01L27/11582 , G11C16/06 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/04 , H01L29/16 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.
Abstract translation: 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。
-
公开(公告)号：US09129859B2
公开(公告)日：2015-09-08
申请号：US13786925
申请日：2013-03-06
Applicant: Intel Corporation
Inventor： Haitao Liu , Chandra V. Mouli , Krishna K. Parat , Jie Sun , Guangyu Huang
IPC: H01L29/76 , H01L27/115 , H01L29/66 , H01L29/788 , H01L29/792
CPC classification number: H01L27/11582 , G11C16/06 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/04 , H01L29/16 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.
Abstract translation: 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。
-
公开(公告)号：US12001280B2
公开(公告)日：2024-06-04
申请号：US17133995
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Krishna K. Parat , Ravi H. Motwani , Rohit S. Shenoy , Ali Khakifirooz
CPC classification number: G06F11/1068 , G11C11/5621 , G11C16/26 , G11C16/0483
Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.
-
公开(公告)号：US20170117049A1
公开(公告)日：2017-04-27
申请号：US14922611
申请日：2015-10-26
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Akira Goda , Pranav Kalavade , Krishna K. Parat , Hiroyuki Sanda
CPC classification number: G11C16/16 , G11C16/0441 , G11C16/0458 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/3427 , G11C16/3477
Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.
-
Patent Agency Ranking
公开(公告)号：US20160336073A1
公开(公告)日：2016-11-17
申请号：US15050871
申请日：2016-02-23
Applicant: Intel Corporation
Inventor： Krishna K. Parat , Pranav Kalavade , Koichi Kawai , Akira Goda
CPC classification number: G11C16/16 , G11C8/12 , G11C16/04 , G11C16/3409 , G11C16/3445
Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify
Abstract translation: 擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败 验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败
-
17.发明授权公开(公告)号：US09418000B2
公开(公告)日：2016-08-16
申请号：US14579971
申请日：2014-12-22
Applicant: Intel Corporation
Inventor： Shyam Sunder Raghunathan , Iwen Chao , Xin Guo , Pranav Kalavade , Krishna K. Parat , Feng Zhu
CPC classification number: G06F12/0246 , G06F11/1084 , G06F2212/7211 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/32 , G11C16/349 , G11C16/3495 , G11C29/021 , G11C29/028
Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.
Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。
-
公开(公告)号：US09305654B2
公开(公告)日：2016-04-05
申请号：US13719558
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Krishna K. Parat , Pranav Kalavade , Koichi Kawai , Akira Goda
CPC classification number: G11C16/16 , G11C8/12 , G11C16/04 , G11C16/3409 , G11C16/3445
Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.
Abstract translation: 擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败 验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败。
-
公开(公告)号：US09099183B2
公开(公告)日：2015-08-04
申请号：US14139219
申请日：2013-12-23
Applicant: Intel Corporation
Inventor： Charan Srinivasan , Pranav Kalavade , Shyam Sunder Raghunathan , Krishna K. Parat
CPC classification number: G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/28 , G11C16/3454
Abstract: Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.
Abstract translation: 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。
-
公开(公告)号：US20200098770A1
公开(公告)日：2020-03-26
申请号：US16412373
申请日：2019-05-14
Applicant: Intel Corporation
Inventor： Haitao Liu , Guangyu Huang , Krishna K. Parat , Shrotri B. Kunal , Srikant Jayanti
IPC: H01L27/11524 , H01L27/11521 , H01L27/11568 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/51
Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.
-
-
-
-
-
-
-
-
-
Search Results
24
records
(took 0.018 seconds)
