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    Stacked scalable voltage regulator module for platform area miniaturization
    12.
    发明授权
    Stacked scalable voltage regulator module for platform area miniaturization 有权

    公开(公告)号：US11343906B2

    公开(公告)日：2022-05-24

    申请号：US16988759

    申请日：2020-08-10

    Applicant: Intel Corporation

    Inventor： Tai Loong Wong ,  Fern Nee Tan ,  Tin Poay Chuah ,  Min Suet Lim ,  Siang Yeong Tan

    IPC: H05K1/02 ,  H05K1/14

    Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.

    ELECTROMAGNETIC INTERFERENCE SHIELDING ENCLOSURE WITH THERMAL CONDUCTIVITY
    13.
    发明申请
    ELECTROMAGNETIC INTERFERENCE SHIELDING ENCLOSURE WITH THERMAL CONDUCTIVITY 有权

    公开(公告)号：US20210153340A1

    公开(公告)日：2021-05-20

    申请号：US17127407

    申请日：2020-12-18

    Applicant: Intel Corporation

    Inventor： Jaejin Lee ,  James Panakkal ,  Min Suet Lim ,  Aiswarya M. Pious

    IPC: H05K1/02 ,  H05K9/00

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to EMI shielding and thermal conduction without using any surface area of a PCB. Embodiments of the EMI shield may include a planar top, with one or more walls extending from the planar top to a bottom surface of the PCB, the PCB having a top surface disposed between the bottom surface of the PCB and the planar top. A ground of the PCB may electrically couple with the one or more walls. The bottom of the walls may couple with an EMI gasket applied to a bottom chassis to increase the volume of EMI shielding. Other embodiments may be described and/or claimed.

    Semiconductor package having integrated stiffener region
    15.
    发明授权
    Semiconductor package having integrated stiffener region 有权

    公开(公告)号：US10923415B2

    公开(公告)日：2021-02-16

    申请号：US16328231

    申请日：2016-09-14

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Shawna M. Liff ,  Feras Eid

    IPC: H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538

    Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.

    Capacitive interconnect in a semiconductor package
    16.
    发明授权
    Capacitive interconnect in a semiconductor package 有权

    公开(公告)号：US10609813B2

    公开(公告)日：2020-03-31

    申请号：US15182091

    申请日：2016-06-14

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Min Suet Lim ,  Fern Nee Tan ,  Khang Choong Yong ,  Jiun Hann Sir

    IPC: H05K1/14 ,  H01L23/498 ,  H01G4/33 ,  H01G4/228 ,  H01G4/12 ,  H05K1/02 ,  H01L21/48 ,  H01L23/50

    Abstract: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.

    INTEGRATED CIRCUIT PACKAGES
    18.
    发明申请
    INTEGRATED CIRCUIT PACKAGES 审中-公开

    公开(公告)号：US20190096833A1

    公开(公告)日：2019-03-28

    申请号：US15713660

    申请日：2017-09-24

    Applicant: Intel Corporation

    Inventor： Min Suet Lim ,  Jiun Hann Sir ,  Eng Huat Eh Goh ,  Mooi Ling Chang

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31

    Abstract: Substrateless integrated circuit (IC) packages having a die with direct diagonal connections, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include: a die having a face with a plurality of contacts thereon, a dielectric layer in contact with the face, and a conductive pathway extending diagonally through the dielectric layer and coupling to an individual contact of the plurality of contacts on the die. In some embodiments, a conductive pathway may fan out to translate the contacts from a more dense layout to a less dense layout. In some embodiments, a conductive pathway may fan in to translate the contacts from a less dense layout to a more dense layout. In some embodiments, the dielectric layer and the conductive pathway may extend beyond the footprint of the die on one or more edges.

    METHODS AND APPARATUS FOR ALLOCATING A WORKLOAD TO AN ACCELERATOR USING MACHINE LEARNING
    19.
    发明申请
    METHODS AND APPARATUS FOR ALLOCATING A WORKLOAD TO AN ACCELERATOR USING MACHINE LEARNING 审中-公开

    公开(公告)号：US20190050265A1

    公开(公告)日：2019-02-14

    申请号：US16146845

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

    IPC: G06F9/50 ,  G06N3/08 ,  G06K9/62 ,  G06F11/30 ,  G06N3/04

    Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

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