公开(公告)号：US20170186697A1

公开(公告)日：2017-06-29

申请号：US14757965

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Rajendra Dias ,  Takashi Kumamoto ,  Yoshishiro Tomita ,  Mitul Modi ,  Joshua Heppner ,  Eric Li

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3135 ,  H01L25/16 ,  H01L2224/73204

Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.

公开(公告)号：US12261150B2

公开(公告)日：2025-03-25

申请号：US18399189

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US12040246B2

公开(公告)日：2024-07-16

申请号：US17033080

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488 ,  H01L21/60

CPC classification number: H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US20230089494A1

公开(公告)日：2023-03-23

申请号：US17482311

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Srinivas V. Pietambaram ,  Mitul Modi

IPC: G02B6/43 ,  G02B6/42

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer having a first surface and an opposing second surface, wherein the first layer includes an insulating material, wherein the PIC has an active side, an opposing backside, and a lateral side substantially perpendicular to the active side and backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an integrated circuit (IC) in a second layer at the second surface of the first layer, wherein the IC is electrically coupled to the active side of the PIC; and an optical component, having a reflector, optically coupled to the lateral side of the PIC and extending at least partially through the insulating material in the first layer along the lateral side of the PIC.

公开(公告)号：US11611164B2

公开(公告)日：2023-03-21

申请号：US16454439

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Zhenguo Jiang ,  Omkar Karhade ,  Sri Chaitra Chavali ,  William Lambert ,  Zhichao Zhang ,  Mitul Modi

IPC: H01R12/72 ,  H01R12/77 ,  H01R13/40 ,  H01R13/24 ,  H01R13/6471 ,  H01R107/00

Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.

公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US11328968B2

公开(公告)日：2022-05-10

申请号：US16463638

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220102231A1

公开(公告)日：2022-03-31

申请号：US17032583

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L25/065

Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.