公开(公告)号：US20180212057A1

公开(公告)日：2018-07-26

申请号：US15747111

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Patrick H. KEYS

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.

公开(公告)号：US20180145063A1

公开(公告)日：2018-05-24

申请号：US15574813

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Patrick MORROW ,  Steven M. BURNS

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit layout is described that uses a library cells with alternating conducting lines. One embodiment includes a first cell and a second cell, the second cell being adjacent to the first cell. The first cell has a first plurality of conductive lines, a first portion of the first plurality having line ends that are a first distance from the second cell. The second cell has a second plurality of conductive lines, the conductive lines being parallel to and aligned with the conductive lines in the first cell, a second portion of the second plurality having line ends that are a second distance from the first cell. The first distance is shorter than the second distance.

公开(公告)号：US20170186855A1

公开(公告)日：2017-06-29

申请号：US15461427

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Anand S. Murthy ,  Robert S. CHAU ,  Patrick MORROW ,  Chia-Hong JAN ,  Paul PACKAN

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

公开(公告)号：US20170011929A1

公开(公告)日：2017-01-12

申请号：US15120720

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Patrick MORROW ,  Donald NELSON

IPC: H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/3081 ,  H01L21/76802 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.

Abstract translation: 使用第一光刻工艺在衬底上形成包括第一组栅格线和第二组栅格线的栅格。 第一组栅格线和第二组栅格线中的至少一个被选择性地图案化以使用第二光刻工艺限定垂直器件特征。

公开(公告)号：US20250107181A1

公开(公告)日：2025-03-27

申请号：US18972346

申请日：2024-12-06

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Mauro KOBRINSKY ,  Patrick MORROW ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/84 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.

公开(公告)号：US20250107061A1

公开(公告)日：2025-03-27

申请号：US18372521

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Seenivasan SUBRAMANIAM ,  Anandkumar MAHADEVAN PILLAI

IPC: H10B10/00 ,  H01L23/528

Abstract: Structures having stacked transistors with backside access are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer including first, second, third and fourth stacks of nanowires and corresponding first, second, third and fourth overlying gate lines, and the device layer including first, second, third, fourth and fifth source or drain structures and corresponding overlying trench contacts alternating with the stacks of nanowires and the overlying gate lines, and one or more metallization layers above the device layer. A backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure isolated from a top portion of the third source or drain structure.

公开(公告)号：US20230238436A1

公开(公告)日：2023-07-27

申请号：US18130824

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY

IPC: H01L29/417

CPC classification number: H01L29/41741 ,  H01L29/41775

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US20230132053A1

公开(公告)日：2023-04-27

申请号：US18087129

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Patrick MORROW

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/12

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US20220254754A1

公开(公告)日：2022-08-11

申请号：US17728813

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20210407999A1

公开(公告)日：2021-12-30

申请号：US16913796

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.