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    Ramping inhibit voltage during memory programming
    13.
    发明授权
    Ramping inhibit voltage during memory programming 有权

    公开(公告)号：US10658053B2

    公开(公告)日：2020-05-19

    申请号：US15715980

    申请日：2017-09-26

    Applicant: Intel Corporation

    Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

    Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

    Predictive count fail byte (CFBYTE) for non-volatile memory
    15.
    发明授权
    Predictive count fail byte (CFBYTE) for non-volatile memory 有权

    公开(公告)号：US10141071B2

    公开(公告)日：2018-11-27

    申请号：US14998119

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Shantanu R. Rajwade ,  Pranav Kalavade

    IPC: G11C29/38 ,  G11C5/14 ,  G11C29/44

    Abstract: Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.

    CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR MEMORY DEVICES
    18.
    发明申请
    CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR MEMORY DEVICES 有权

    公开(公告)号：US20220310178A1

    公开(公告)日：2022-09-29

    申请号：US17213150

    申请日：2021-03-25

    Applicant: Intel Corporation

    Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/10

    Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

    Segmented erase in memory
    19.
    发明授权
    Segmented erase in memory 有权

    公开(公告)号：US10453535B2

    公开(公告)日：2019-10-22

    申请号：US14922611

    申请日：2015-10-26

    Applicant: Intel Corporation

    Inventor： Shantanu R. Rajwade ,  Akira Goda ,  Pranav Kalavade ,  Krishna K. Parat ,  Hiroyuki Sanda

    IPC: G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/34

    Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

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