公开(公告)号：US20230298953A1

公开(公告)日：2023-09-21

申请号：US17699139

申请日：2022-03-20

Applicant: Intel Corporation

Inventor： Pouya Talebbeydokhti ,  Mohan Prashanth Javare Gowda ,  Sonja Koller ,  Stephan Stoeckl ,  Thomas Wagner ,  Wolfgang Molzer

IPC: H01L23/053 ,  H01L23/00 ,  H01L25/10 ,  H01L23/06 ,  H01L23/10

CPC classification number: H01L23/053 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/06 ,  H01L23/10 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2924/1611 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1632

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

公开(公告)号：US11646498B2

公开(公告)日：2023-05-09

申请号：US16414356

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Kilian Roth ,  Sonja Koller ,  Josef Hagn ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/34 ,  H01Q13/18 ,  H01L23/66 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01Q1/22

CPC classification number: H01Q13/18 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/2283 ,  H01L2223/6616 ,  H01L2223/6677

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

公开(公告)号：US11456116B2

公开(公告)日：2022-09-27

申请号：US16474015

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Bernd Waidhas ,  Sonja Koller ,  Reinhard Mahnkopf ,  Georg Seidemann

IPC: H01F27/24 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L27/01 ,  H01L49/02

Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.

公开(公告)号：US11134573B2

公开(公告)日：2021-09-28

申请号：US16642801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US20200352035A1

公开(公告)日：2020-11-05

申请号：US16642801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US09299672B2

公开(公告)日：2016-03-29

申请号：US14280110

申请日：2014-05-16

Applicant: INTEL CORPORATION

Inventor： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

公开(公告)号：US20230317681A1

公开(公告)日：2023-10-05

申请号：US17709481

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sonja Koller ,  Vishnu Prasad ,  Bernd Waidhas ,  Eduardo De Mesa ,  Lizabeth Keser ,  Thomas Wagner ,  Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Jan Proschwitz

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/427 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3736 ,  H01L23/427 ,  H01L24/16 ,  H01L24/32 ,  H01L23/367 ,  H01L25/50 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2224/73203 ,  H01L2224/32245 ,  H01L2224/16146 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L24/14 ,  H01L24/73

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

公开(公告)号：US20230317551A1

公开(公告)日：2023-10-05

申请号：US17708890

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Vishnu Prasad ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser ,  Thomas Wagner ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz

IPC: H01L23/373 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/3736 ,  H01L25/18 ,  H01L21/4896

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

公开(公告)号：US11764187B2

公开(公告)日：2023-09-19

申请号：US16641241

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20230268291A1

公开(公告)日：2023-08-24

申请号：US17679189

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Stephan Stoeckl ,  Sonja Koller ,  Wolfgang Molzer ,  Thomas Wagner ,  Pouya Talebbeydokhti

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/552

Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.