公开(公告)号：US20140232519A1

公开(公告)日：2014-08-21

申请号：US13772651

申请日：2013-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ira L. Allen ,  Lawrence A. Clevenger ,  Kevin S. Petrarca ,  Carl J. Radens

IPC: G06Q30/02

CPC classification number: G06Q30/0283 ,  G06Q10/08

Abstract: In a method for controlling pricing of a product, a radio frequency identification (RFID) tag having at least one processor is attached to a monitored product. A value indicative of a degree of exposure to an environmental condition is obtained. The obtained value is compared with a predetermined value range. A price of the monitored product is adjusted when the result of the comparison falls outside the predetermined value range.

Abstract translation: 在用于控制产品定价的方法中，具有至少一个处理器的射频识别（RFID）标签被附加到被监视的产品。 获得表示暴露于环境条件的程度的值。 将所获得的值与预定值范围进行比较。 当比较结果超出预定值范围时，调整被监视产品的价格。

公开(公告)号：US20140065783A1

公开(公告)日：2014-03-06

申请号：US14073159

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L29/66575 ,  H01L21/28017 ,  H01L21/283 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78

Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Abstract translation: 包括清除材料和电介质材料的至少一层沉积在栅叠层上，随后进行各向异性蚀刻以形成含氧清除材料的栅间隔物。 含氧清除材料的栅极间隔物可以是包含清除纳米颗粒的栅极间隔物或含有扫气岛的栅极间隔物。 清除材料以防止栅极电极和栅极电介质下方的半导体材料之间的电短路的方式分布在含氧清除材料的栅极间隔物内。 清扫材料主动地清除从可以形成在含氧清除材料的栅极间隔物周围形成的介电栅极隔离物的上方或外部扩散到栅极电介质的氧。

公开(公告)号：US10707224B2

公开(公告)日：2020-07-07

申请号：US15988828

申请日：2018-05-24

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/11568 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/40 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

公开(公告)号：US10395984B2

公开(公告)日：2019-08-27

申请号：US15070242

申请日：2016-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin C. Backes ,  Brian A. Cohen ,  Joyeeta Nag ,  Carl J. Radens

IPC: H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.

公开(公告)号：US20190172748A1

公开(公告)日：2019-06-06

申请号：US16257221

申请日：2019-01-25

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234

Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US20170365590A1

公开(公告)日：2017-12-21

申请号：US15695198

申请日：2017-09-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20170179244A1

公开(公告)日：2017-06-22

申请号：US15396796

申请日：2017-01-02

Applicant: International Business Machines Corporation

Inventor： Carl J. Radens ,  Richard Q. Williams

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/41766 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53257 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/458 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359

Abstract: A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.

公开(公告)号：US20160020105A1

公开(公告)日：2016-01-21

申请号：US14871157

申请日：2015-09-30

Applicant: International Business Machines Corporation ,  STMicroelectronics Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Edem Wornyo ,  Yiheng Xu ,  John Zhang

IPC: H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/0661 ,  H01L21/02071 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66621 ,  H01L29/66795 ,  H01L51/0525

Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

公开(公告)号：US20150287809A1

公开(公告)日：2015-10-08

申请号：US14519596

申请日：2014-10-21

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Carl J. Radens ,  Sudesh Saroop

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/31144 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights.

Abstract translation: 半导体翅片形成在基板的顶表面上。 介电材料通过各向异性沉积沉积在半导体鳍片和衬底的顶表面上。 在衬底的顶表面上的电介质材料层被图案化，使得电介质材料层的剩余部分横向包围至少一个半导体鳍片的每个底部，同时不接触至少一个第二半导体鳍片。 半导体鳍片的顶表面上的电介质材料部分可以任选地被去除。 每个第一半导体鳍片具有比至少一个第二半导体鳍片更小的沟道高度。 可以采用第一和第二半导体鳍片来提供具有不同通道高度的鳍式场效应晶体管。

公开(公告)号：US20150287743A1

公开(公告)日：2015-10-08

申请号：US14243398

申请日：2014-04-02

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Carl J. Radens ,  Sudesh Saroop

IPC: H01L27/12 ,  H01L21/311 ,  H01L21/28 ,  H01L29/04 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/31144 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights.