公开(公告)号：US20190096462A1

公开(公告)日：2019-03-28

申请号：US15717023

申请日：2017-09-27

Applicant: International Business Machines Corporation

Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC: G11C11/22 ,  H03K19/177

CPC classification number: G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/54 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H03K19/1776

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US11889773B2

公开(公告)日：2024-01-30

申请号：US18172385

申请日：2023-02-22

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Injo Ok ,  Jin Ping Han ,  Timothy Mathew Philip ,  Matthew Joseph BrightSky ,  Nicole Saulnier

IPC: G11C11/00 ,  H10N70/20 ,  G11C11/54 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  G06N3/065

CPC classification number: H10N70/231 ,  G11C11/54 ,  G11C13/0004 ,  H10B63/24 ,  H10N70/826 ,  H10N70/8413 ,  G06N3/065 ,  G11C2213/72

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

公开(公告)号：US11366874B2

公开(公告)日：2022-06-21

申请号：US16198945

申请日：2018-11-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dennis Newns ,  Paul Solomon ,  Xiaodong Cui ,  Jin Ping Han ,  Xin Zhang

IPC: G06F17/10 ,  G06F9/30 ,  G06N3/08 ,  G06F9/38 ,  G06K9/62 ,  G06N3/063

Abstract: Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

公开(公告)号：US11244999B2

公开(公告)日：2022-02-08

申请号：US16502783

申请日：2019-07-03

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L49/02 ,  H01L27/11507 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/283 ,  H01B3/10

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

公开(公告)号：US11107835B2

公开(公告)日：2021-08-31

申请号：US16668433

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin Ping Han ,  Ramachandran Muralidhar ,  Paul M. Solomon ,  Dennis M. Newns ,  Martin M. Frank

IPC: H01L27/11585 ,  H01L27/24 ,  H01L27/11587 ,  G11C11/56 ,  G11C11/22

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

公开(公告)号：US10686040B2

公开(公告)日：2020-06-16

申请号：US16395084

申请日：2019-04-25

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L27/088 ,  H01L29/12 ,  H01L29/06 ,  H01L27/085 ,  H01L23/52 ,  H01L21/8234

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US20200066755A1

公开(公告)日：2020-02-27

申请号：US16668433

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin Ping Han ,  Ramachandran Muralidhar ,  Paul M. Solomon ,  Dennis M. Newns ,  Martin M. Frank

IPC: H01L27/11585 ,  G11C11/56 ,  H01L27/24 ,  G11C11/22 ,  H01L27/11587

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

公开(公告)号：US20180090596A1

公开(公告)日：2018-03-29

申请号：US15277722

申请日：2016-09-27

Applicant: International Business Machines Corporation

Inventor： Victor Chan ,  Jin Ping Han

IPC: H01L29/66 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L29/42376 ,  H01L29/4966

Abstract: A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height. A channel region is interposed between opposing source/drain regions, and a gate stack is atop the semiconductor substrate. The gate stack includes an electrically conductive gate atop the channel region. The electrically conductive gate includes sidewalls extending between a base and an upper surface to define a gate height. A gate length of the electrically conductive gate continuously increases as the gate height increases from the base to the upper surface.

公开(公告)号：US09748358B2

公开(公告)日：2017-08-29

申请号：US14973780

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Victor Chan ,  Jin Ping Han ,  Shangbin Ko

IPC: H01L21/28 ,  H01L21/283 ,  H01L29/66 ,  H01L23/535 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/2253 ,  H01L21/283 ,  H01L23/535 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7845

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

公开(公告)号：US20250008848A1

公开(公告)日：2025-01-02

申请号：US18344194

申请日：2023-06-29

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Timothy Mathew Philip ,  Jin Ping Han ,  Ching-Tzu Chen

IPC: H10N70/00 ,  C09K5/06 ,  H10B63/10 ,  H10N70/20

Abstract: A phase change memory device that includes a composite phase change material layer comprising a mixture of a dispersed phase of a projection material of a first resistivity, and a matrix of a phase-change material of a second resistivity or third resistivity dependent on phase. The first resistivity of the projection material has a resistance that is greater than the second resistance for the phase change material, and is less than the third resistance of the phase change material. The phase change memory device further includes a first electrode; and a second electrode on opposing faces of the composite phase change material layer. The projection material forms a percolated conducting path from the first electrode to the second electrode.