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公开(公告)号：US09329664B2
公开(公告)日：2016-05-03
申请号：US13966414
申请日：2013-08-14
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
CPC classification number: G06F1/3243 , G06F1/3228 , G06F1/3234 , G06F1/3275 , G06F1/3278 , G06F3/0656 , G06F9/3877 , G06F9/44 , G06F9/4893 , G06F13/00 , G06F13/1663 , G06F2212/312 , Y02D10/152 , Y02D10/24 , Y02D50/20
Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.
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公开(公告)号：US09298654B2
公开(公告)日：2016-03-29
申请号：US13837909
申请日：2013-03-15
Applicant: International Business Machines Corporation
Inventor： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Martin Ohmacht , Krishnan Sugavanam
IPC: G06F13/36 , G06F13/00 , G06F13/28 , G06F13/364
CPC classification number: G06F13/364 , G06F9/3826 , G06F13/28 , G06F21/72 , H01L25/18 , H01L2924/0002 , H04L2209/125 , Y02D10/14 , H01L2924/00
Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.
Abstract translation: 实施例包括用于旁路有源存储器件中的数据的方法。 该方法包括：请求者确定尚未传送给设保者的授权人的传送次数，根据满足阈值的传送次数，向互连网请求旁路路径用于传送，并通过 基于请求的设保人的旁路路径，互连网络根据请求授予设保人的控制权。 该方法还包括互连网络，其基于事件请求对设保人的控制，并且经由互连网络从其他请求者传送延迟的传输，延迟的传送由于授权者先前由请求者控制而延迟，基于控制进行通信 的设保人被改回互连网络。
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公开(公告)号：US09250916B2
公开(公告)日：2016-02-02
申请号：US13795435
申请日：2013-03-12
Applicant: International Business Machines Corporation
Inventor： Thomas W. Fox , Bruce M. Fleischer , Hans M. Jacobson , Ravi Nair
CPC classification number: G06F9/3867 , G06F9/30079 , G06F9/3017 , G06F9/30185 , G06F9/3826 , G06F9/3828
Abstract: Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline.
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公开(公告)号：US09104465B2
公开(公告)日：2015-08-11
申请号：US13684657
申请日：2012-11-26
Applicant: International Business Machines Corporation
Inventor： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
CPC classification number: G06F9/46 , G06F9/3877 , G06F9/5044 , G06F2209/509 , Y02D10/22
Abstract: According to one embodiment of the present invention, a computer system for executing a task includes a main processor, a processing element and memory. The computer system is configured to perform a method including receiving, at the processing element, the task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request including execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.
Abstract translation: 根据本发明的一个实施例，用于执行任务的计算机系统包括主处理器，处理元件和存储器。 计算机系统被配置为执行一种方法，包括在处理元件处接收来自主处理器的任务，由处理元件执行由该任务指定的指令，由处理元件确定功能是 在所述主处理器上执行所述功能是所述任务的一部分，由所述处理元件向所述主处理器发送请求以执行所述请求，所述请求包括所述功能的执行，并且在所述处理元件处接收所述处理元件的指示， 主处理器已完成执行请求指定的功能。
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公开(公告)号：US09104464B2
公开(公告)日：2015-08-11
申请号：US13669877
申请日：2012-11-06
Applicant: International Business Machines Corporation
Inventor： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
CPC classification number: G06F9/46 , G06F9/3877 , G06F9/5044 , G06F2209/509 , Y02D10/22
Abstract: According to one embodiment of the present invention, a method for operating a computer system including a main processor, a processing element and memory is provided. The method includes receiving, at the processing element, a task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request comprising execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.
Abstract translation: 根据本发明的一个实施例，提供了一种用于操作包括主处理器，处理元件和存储器的计算机系统的方法。 该方法包括在处理单元处接收来自主处理器的任务，由处理单元执行由任务指定的指令，由处理单元确定要在主处理器上执行功能， 所述功能是所述任务的一部分，由所述处理元件发送对所述主处理器执行的请求，所述请求包括所述功能的执行，并且在所述处理元件处接收到所述主处理器已完成所述主处理器的执行的指示 函数由请求指定。
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Patent Agency Ranking
公开(公告)号：US20140195744A1
公开(公告)日：2014-07-10
申请号：US13761252
申请日：2013-02-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC: G06F13/16
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0625 , G06F3/0673 , G06F9/4881 , G06F13/1626 , G06F13/1663 , G06F13/18 , Y02D10/14
Abstract: According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request.
Abstract translation: 根据一个实施例，提供了一种存储器件。 存储器件包括耦合到交叉开关互连的处理元件。 处理元件被配置为向交叉开关互连发送包括优先级值的存储器访问请求。 交叉开关互连被配置为将存储器访问请求路由到与存储器访问请求相关联的存储器控制器。 存储器控制器耦合到存储器和交叉开关互连。 存储器控制器包括队列，并被配置为将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求并执行下一个存储器 基于最高优先级存储器访问请求的访问请求。
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公开(公告)号：US20180260326A1
公开(公告)日：2018-09-13
申请号：US15451858
申请日：2017-03-07
Applicant: International Business Machines Corporation
Inventor： Gregory W. Alexander , Brian D. Barrick , Thomas W. Fox , Christian Jacobi , Anthony Saporito , Somin Song , Aaron Tsai
IPC: G06F12/0811 , G06F12/0804 , G06F12/0875
CPC classification number: G06F12/0811 , G06F9/30047 , G06F12/0804 , G06F12/0813 , G06F12/0859 , G06F12/0875 , G06F2212/452 , G06F2212/60 , G06F2212/62
Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.
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公开(公告)号：US20160364364A1
公开(公告)日：2016-12-15
申请号：US14948656
申请日：2015-11-23
Applicant: International Business Machines Corporation
Inventor： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC: G06F15/173 , G06F13/40 , G06F13/28 , G06F13/42
CPC classification number: G06F13/362 , G06F13/287 , G06F13/4022 , G06F13/4068 , G06F13/4282 , G06F15/17337
Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.
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公开(公告)号：US20160364352A1
公开(公告)日：2016-12-15
申请号：US14739014
申请日：2015-06-15
Applicant: International Business Machines Corporation
Inventor： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC: G06F13/362 , G06F13/40
CPC classification number: G06F13/362 , G06F13/287 , G06F13/4022 , G06F13/4068 , G06F13/4282 , G06F15/17337
Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.
Abstract translation: 提供处理元件之间数据的直接通信。 一个方面包括由第一处理单元通过一个处理间链接总线发送数据。 数据经由数据交换部件发往另一个处理元件，该数据交换部件经由设置在第一处理元件和第二处理元件的相应复用器之间的通信线路耦合在第一处理元件和第二处理元件之间。 另一方面包括由数据交换组件确定数据是否已经在数据交换元件处被接收。 如果是这样，则在数据交换组件的寄存器中设置指示符，并将数据转发到另一处理单元。 设置指示灯使第一个处理元件停止。 如果没有接收到数据，则在数据交换组件等待接收数据的同时处理元件停止。
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公开(公告)号：US20160363916A1
公开(公告)日：2016-12-15
申请号：US14736758
申请日：2015-06-11
Applicant: International Business Machines Corporation
Inventor： Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Bryan S. Rosenburg
IPC: G05B15/02
CPC classification number: G05B15/02
Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.
Abstract translation: 计算机检测进程访问影子控制页面的请求，其中阴影控制页面允许对一个或多个设备的进程访问。 计算机将阴影控制页面和一个密钥分配给与请求相关联的进程。 计算机通过所分配的影子控制页面检测该过程的请求，以从一个或多个设备创建设备子集。 计算机将详细描述设备子集与所分配的密钥之间的关联的信息输入到子集定义表中，其中子集定义表包括一个或多个密钥和一个或多个相应的子集。
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