公开(公告)号：US20140159166A1

公开(公告)日：2014-06-12

申请号：US13708126

申请日：2012-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Effendi LEOBANDUNG ,  Tenko YAMASHITA ,  Chun-chen YEH

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged.

Abstract translation: 通过在绝缘层上包含含硅层的基板上形成硬掩模层来形成FinFET结构。 硬掩模层包括含硅层上的第一层，第二层和第三层。 翅片阵列由硬掩模层和含硅层形成。 形成盖子，其覆盖翅片阵列中的每一个的一部分而不是全部长度。 该部分覆盖阵列中的每个翅片。 门限定栅极两侧的源/漏区。 隔离件形成在栅极的每一侧上，形成间隔物以进行以从源极/漏极区域中的鳍片的部分去除第三层。 硬掩模层的第二层从源极/漏极区域中的鳍片的部分去除，并且源极/漏极区域中的鳍片被合并。

公开(公告)号：US20200152756A1

公开(公告)日：2020-05-14

申请号：US16188612

申请日：2018-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew GREENE ,  Dechao GUO ,  Tenko YAMASHITA ,  Veeraraghavan S. BASKER ,  Robert ROBISON ,  Ardasheir RAHMAN

IPC: H01L29/45 ,  H01L21/3205

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

公开(公告)号：US20200091314A1

公开(公告)日：2020-03-19

申请号：US16668496

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L29/49 ,  H01L23/485 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

公开(公告)号：US20190214456A1

公开(公告)日：2019-07-11

申请号：US16359292

申请日：2019-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Christopher J. PENNY ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L28/88 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53228 ,  H01L28/60 ,  H01L28/82

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

公开(公告)号：US20190148554A1

公开(公告)日：2019-05-16

申请号：US16245861

申请日：2019-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/485 ,  H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L21/311

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

公开(公告)号：US20180076094A1

公开(公告)日：2018-03-15

申请号：US15813277

申请日：2017-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/823481 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/785

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

公开(公告)号：US20170084684A1

公开(公告)日：2017-03-23

申请号：US15260688

申请日：2016-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/87 ,  H01L28/88 ,  H01L28/91 ,  H01L28/92

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

公开(公告)号：US20140264602A1

公开(公告)日：2014-09-18

申请号：US14031118

申请日：2013-09-19

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. BASKER ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Tenko YAMASHITA ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7855

Abstract: Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon.

公开(公告)号：US20140264601A1

公开(公告)日：2014-09-18

申请号：US14031108

申请日：2013-09-19

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. BASKER ,  Chun-chen YEH ,  Tenko YAMASHITA

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/1211 ,  H01L21/02107 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0337 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  Y10S438/933

Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.

公开(公告)号：US20140151850A1

公开(公告)日：2014-06-05

申请号：US14174887

申请日：2014-02-07

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. BASKER ,  Richard Q. WILLIAMS

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/108 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.

Abstract translation: 方法和结构针对具有高电导电极的eDRAM细胞。 该方法包括在半导体衬底上形成上层并在上层形成开口。 该方法还包括在半导体衬底中形成与开口对准的沟槽。 该方法还包括通过将具有电偏压的金属水溶液施加到半导体衬底的背面，在沟槽的所有暴露表面上形成金属板。