公开(公告)号：US10317338B2

公开(公告)日：2019-06-11

申请号：US15716598

申请日：2017-09-27

Applicant: Infineon Technologies AG

Inventor： Naveen Goud Ganagona ,  Moriz Jelinek ,  Helmut Oefner ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: G01N21/3563 ,  G01N21/35

Abstract: A method of determining the carbon content in a silicon sample may include: generating electrically active polyatomic complexes within the silicon sample. Each polyatomic complex may include at least one carbon atom. The method may further include: determining a quantity indicative of the content of the generated polyatomic complexes in the silicon sample, and determining the carbon content in the silicon sample from the determined quantity.

公开(公告)号：US20180102423A1

公开(公告)日：2018-04-12

申请号：US15831247

申请日：2017-12-04

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Moriz Jelinek ,  Johannes Laven ,  Helmut Oefner ,  Werner Schustereder

IPC: H01L29/739 ,  H01L29/36 ,  H01L29/10 ,  H01L21/66 ,  H01L21/263 ,  H01L21/324

CPC classification number: H01L29/7395 ,  H01L21/263 ,  H01L21/324 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes at least one transistor structure. The at least one transistor structure includes an emitter or source terminal, and a collector or drain terminal. A carbon concentration within a semiconductor substrate region located between the emitter or source terminal and the collector or drain terminal varies between the emitter or source terminal and the collector or drain terminal.

公开(公告)号：US20160322198A1

公开(公告)日：2016-11-03

申请号：US14701320

申请日：2015-04-30

Applicant: Infineon Technologies AG

Inventor： Ewald Wiltsche ,  Peter Zupan ,  Werner Schustereder ,  Moriz Jelinek ,  Robert Eberwein ,  Friedrich Kroener

IPC: H01J37/317 ,  H01L21/67 ,  C23C14/16 ,  C23C14/34 ,  H01J37/08 ,  C23C14/48

CPC classification number: H01J37/3171 ,  C23C14/48 ,  H01J37/08 ,  H01J2237/081 ,  H01J2237/0822

Abstract: An ion source for an implanter includes a first solid state source electrode disposed in an ion source chamber. The first solid state source electrode includes a source material coupled to a first negative potential node. A second solid state source electrode is disposed in the ion source chamber. The second solid state source electrode includes the source material coupled to a second negative potential node, and the first solid state source electrode and the second solid state source electrode are configured to produce ions to be implanted by the implanter.

Abstract translation: 用于注入机的离子源包括设置在离子源室中的第一固态源电极。 第一固态源极包括耦合到第一负电位节点的源极材料。 第二固态源电极设置在离子源室中。 第二固体源电极包括耦合到第二负电位节点的源极材料，并且第一固态源极电极和第二固态源极电极被配置为产生待被注入器植入的离子。

公开(公告)号：US20160211336A1

公开(公告)日：2016-07-21

申请号：US15081487

申请日：2016-03-25

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Hans-Joachim Schulze ,  Moriz Jelinek ,  Werner Schustereder

IPC: H01L29/32 ,  H01L29/36

CPC classification number: H01L29/32 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/3221 ,  H01L21/324 ,  H01L21/3242 ,  H01L29/04 ,  H01L29/16 ,  H01L29/167 ,  H01L29/36 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/86

Abstract: A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm−3 at a first distance to the first surface and does not fall below 1E14 cm−3 over at least 60% of an interval between the first surface and the first distance.

Abstract translation: 半导体器件包括具有平行的第一和第二表面并且含有氢的相关供体的半导体本体。 垂直于第一表面的氢相关供体的浓度分布包括在距第一表面的第一距离处的至少1E15cm-3的最大值，并且在间隔的至少60％内不低于1E14cm-3 在第一表面和第一距离之间。

公开(公告)号：US12057316B2

公开(公告)日：2024-08-06

申请号：US17476829

申请日：2021-09-16

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Paul Ellinghaus ,  Axel Koenig ,  Caspar Leendertz ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/265 ,  H01L21/04 ,  H01L29/04 ,  H01L29/16 ,  H01L29/167

CPC classification number: H01L21/047 ,  H01L29/045 ,  H01L29/1608

Abstract: A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a direction or a direction.

公开(公告)号：US20230352531A1

公开(公告)日：2023-11-02

申请号：US18220989

申请日：2023-07-12

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Jaeger ,  Moriz Jelinek ,  Daniel Schloegl ,  Benedikt Stoib

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/322 ,  H01L29/10

CPC classification number: H01L29/0834 ,  H01L29/7395 ,  H01L29/0638 ,  H01L29/66333 ,  H01L21/26513 ,  H01L21/3221 ,  H01L29/1095

Abstract: A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

公开(公告)号：US20210320174A1

公开(公告)日：2021-10-14

申请号：US17217251

申请日：2021-03-30

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Jaeger ,  Moriz Jelinek ,  Daniel Schloegl ,  Benedikt Stoib

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/322 ,  H01L29/66

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.

公开(公告)号：US20200212203A1

公开(公告)日：2020-07-02

申请号：US16723147

申请日：2019-12-20

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Kang Nan Khor ,  Armin Schieber ,  Michael Stadtmueller ,  Wei-Lin Sun

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/423

Abstract: A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method includes: generating the trench in the semiconductor substrate; generating an oxide layer over opposing sidewalls of the trench; damaging at least a portion of the oxide layer by ion implantation; coating the oxide layer with an etching mask; generating at least one opening in the etching mask adjacent to one of the opposing sidewalls; and partly removing the oxide layer by etching the oxide layer beneath the etching mask down to an etching depth at the one of the opposing sidewalls by introducing an etching agent into the opening.

公开(公告)号：US10192955B2

公开(公告)日：2019-01-29

申请号：US15718189

申请日：2017-09-28

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Moriz Jelinek ,  Hans-Joachim Schulze ,  Werner Schustereder ,  Michael Stadtmueller

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/739 ,  H01L21/263 ,  H01L21/265 ,  H01L21/322 ,  H01L29/36 ,  H01L29/861 ,  H01L29/167 ,  H01L21/66

Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.

公开(公告)号：US10096677B2

公开(公告)日：2018-10-09

申请号：US15178039

申请日：2016-06-09

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Naveen Goud Ganagona ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L21/263 ,  H01L21/324 ,  H01L21/67 ,  H01L21/66 ,  H01L29/32 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.