公开(公告)号：US10777655B2

公开(公告)日：2020-09-15

申请号：US15859416

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Joseph Steigerwald ,  Jinhong Shin ,  Vinay Chikarmane ,  Christopher P. Auth

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20190164765A1

公开(公告)日：2019-05-30

申请号：US15859412

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Tahir Ghani ,  Atul Madhavan ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US09679845B2

公开(公告)日：2017-06-13

申请号：US15124867

申请日：2014-05-08

Applicant: Intel Corporation

Inventor： Zhanping Chen ,  Andrew W. Yeoh ,  Seongtae Jeong ,  Uddalak Bhattacharya ,  Charles H. Wallace

IPC: H01L23/525 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.

公开(公告)号：US09530740B2

公开(公告)日：2016-12-27

申请号：US14836828

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

公开(公告)号：US12199168B2

公开(公告)日：2025-01-14

申请号：US17849198

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Ilsup Jin ,  Angelo Kandas ,  Michael L Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

公开(公告)号：US12067338B2

公开(公告)日：2024-08-20

申请号：US17585101

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Quan Shi ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sourav Chakravarty ,  Barbara A. Chappell ,  M. Clair Webb

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L27/00 ,  H01L27/11

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US11581419B2

公开(公告)日：2023-02-14

申请号：US17080694

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Joseph Steigerwald ,  Jinhong Shin ,  Vinay Chikarmane ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US10854731B2

公开(公告)日：2020-12-01

申请号：US16537020

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Joseph Steigerwald ,  Jinhong Shin ,  Vinay Chikarmane ,  Christopher P. Auth

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20170011997A1

公开(公告)日：2017-01-12

申请号：US15274175

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract translation: 实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。 本文描述了其它实施例。

公开(公告)号：US09496173B2

公开(公告)日：2016-11-15

申请号：US14137487

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L23/498 ,  H01L23/522 ,  H01L21/68 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract translation: 实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。 本文描述了其它实施例。