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公开(公告)号：US09838967B2
公开(公告)日：2017-12-05
申请号：US14595085
申请日：2015-01-12
Applicant: Intel Corporation
Inventor： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
CPC classification number: H04W52/0225 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3296 , G06F13/4282 , H04L43/0858 , Y02D10/151 , Y02D70/00 , Y02D70/142 , Y02D70/23
Abstract: An apparatus is provided that includes a transceiver to transmit and receive data between an upstream device and the apparatus, and further includes service latency reporting logic coupled to the transceiver to provide a service latency tolerance value of the apparatus to the upstream device, the service latency tolerance value corresponding to an activity state of the apparatus. The service latency tolerance value for an idle activity state can be greater than the service latency tolerance value for an active activity state.
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公开(公告)号：US20170329377A1
公开(公告)日：2017-11-16
申请号：US15668771
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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公开(公告)号：US09541987B2
公开(公告)日：2017-01-10
申请号：US13931807
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Barnes Cooper
IPC: G06F1/32
CPC classification number: G06F1/3268 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D10/154
Abstract: Methods and apparatus relating to generic host-based controller latency are described. In one embodiment, latency information, corresponding to one or more devices, is detected from a host controller that controls access to the one or more devices. Detection of the latency information is performed in response to one or more transactions that are initiated by the host controller. Other embodiments are also claimed and disclosed.
Abstract translation: 描述与通用的基于主机的控制器等待时间有关的方法和装置。 在一个实施例中，从控制对一个或多个设备的访问的主机控制器检测对应于一个或多个设备的等待时间信息。 响应于由主机控制器启动的一个或多个事务来执行等待时间信息的检测。 还要求和公开其它实施例。
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14.发明授权公开(公告)号：US12038854B2
公开(公告)日：2024-07-16
申请号：US17134089
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Jaya L. Jeyaseelan , Barnes Cooper , Abdul R. Ismail
IPC: G06F13/16 , G06F1/3234 , G06T1/20
CPC classification number: G06F13/1668 , G06F1/325 , G06T1/20 , G06F1/3265
Abstract: Techniques for controlling input/output (I/O) power usage are disclosed. In the illustrative embodiment, a power policy engine of a compute device monitors power usage, I/O data transfer rates, and temperature and determines when there should be a change in an I/O power setting. The I/O data transfer requires that the data be handled properly, causing the compute device to expend power on the I/O data transfer. The power policy engine may instruct a device driver, such as a driver of an I/O device, to change a data transfer rate of the I/O device, reducing the power the compute device spends handling I/O.
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公开(公告)号：US20220334620A1
公开(公告)日：2022-10-20
申请号：US17856587
申请日：2022-07-01
Applicant: Intel Corporation
Inventor： Barnes Cooper , Aleksander Magi , Arvind Kumar , Giuseppe Raffa , Wendy March , Marko Bartscherer , Irina Lazutkina , Duck Young Kong , Meng Shi , Vivek Paranjape , Vinod Gomathi Nayagam , Glen J. Anderson
Abstract: Methods and apparatus to operate closed-lid portable computers are disclosed. An example portable compute device includes: a microphone; a speaker; a first camera to face a first direction; and a second camera to face a second direction, the second direction opposite the first direction. The compute device further includes communications circuitry; a first display; a second display separate from the first display; and a hinge to enable the first display to rotate relative to the second display between an open position and a closed position. At least a portion of the second display is capable of being visible when the first display is rotated about the hinge to the closed position. The portion of the second display is multiple times longer in a third direction than in a fourth direction perpendicular to the third direction, the third direction extending parallel to an axis of rotation of the hinge.
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Patent Agency Ranking
公开(公告)号：US11307868B2
公开(公告)日：2022-04-19
申请号：US15639605
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Faraz A. Siddiqi , Barnes Cooper
IPC: G06F9/44 , G06F13/00 , G06F9/455 , G06F9/46 , G06F9/4401
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.
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公开(公告)号：US11132046B2
公开(公告)日：2021-09-28
申请号：US16650782
申请日：2017-12-15
Applicant: Intel Corporation
Inventor： Barnes Cooper , Harinarayanan Seshadri , Rajeev Muralidhar , Noor Mubeen
IPC: G06F1/32 , G06F1/3228 , G06F1/329 , G06F1/3296
Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.
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公开(公告)号：US10571992B2
公开(公告)日：2020-02-25
申请号：US15634805
申请日：2017-06-27
Applicant: INTEL CORPORATION
Inventor： Robert E. Gough , Mazen G. Gedeon , Barnes Cooper , Basavaraj B. Astekar , Sean C. Dardis
IPC: G06F1/32 , G06F1/3234 , G06F1/3231 , G06F1/3293
Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.
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公开(公告)号：US09934047B2
公开(公告)日：2018-04-03
申请号：US14220812
申请日：2014-03-20
Applicant: INTEL CORPORATION
Inventor： Faraz A. Siddiqi , Barnes Cooper
IPC: G06F15/177 , G06F9/44 , G06F13/00 , G06F9/455 , G06F9/46
CPC classification number: G06F9/4406 , G06F9/4418 , G06F9/45558 , G06F9/46 , G06F13/00 , G06F2009/45575
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.
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公开(公告)号：US09766673B2
公开(公告)日：2017-09-19
申请号：US14633438
申请日：2015-02-27
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
CPC classification number: G06F1/263 , G06F1/206 , G06F1/3212 , G06F1/324 , G06F15/00 , Y02D10/126 , Y02D10/16 , Y02D10/174
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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