公开(公告)号：US10421432B2

公开(公告)日：2019-09-24

申请号：US15608297

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Victoria C. Moore ,  Ned M. Smith ,  Digvijay A. Raorane

IPC: B60R25/01 ,  H04L9/32 ,  G07C9/00

Abstract: A user-customizable locking assembly includes a user-customizable key, a user-customizable key receiver, and a key receiver receptacle. Each of the user-customizable key, a user-customizable key receiver, and a key receiver receptacle includes a physical unclonable function (PUF) circuit configured to provide a PUF response in response to receiving a challenge signal. The PUF circuits of the user-customizable key and a user-customizable key receiver include personalization fuses that allow a user to further personalize or change the PUF response produced by the corresponding PUF circuits. The key receiver receptacle also includes anti-theft fuses, which are activated if the user-customizable key receiver is removed from the key receiver receptacle. In use, a protected system may utilize the PUF responses from the each of the PUF circuits to authenticate the user-customizable locking assembly.

公开(公告)号：US20190103361A1

公开(公告)日：2019-04-04

申请号：US15721788

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane ,  Vipul V. Mehta

IPC: H01L23/538 ,  H01L23/12 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/498 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.

公开(公告)号：US20160322344A1

公开(公告)日：2016-11-03

申请号：US15208502

申请日：2016-07-12

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US09397079B2

公开(公告)日：2016-07-19

申请号：US14636016

申请日：2015-03-02

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US12009318B2

公开(公告)日：2024-06-11

申请号：US17714944

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane ,  Ian En Yoon Chin ,  Daniel N. Sobieski

IPC: H01L23/49 ,  H01L21/50 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/50 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/20 ,  H01L23/3121 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US11587851B2

公开(公告)日：2023-02-21

申请号：US17323840

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L23/49 ,  H01L21/76 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US11488880B2

公开(公告)日：2022-11-01

申请号：US16619061

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay A. Raorane

IPC: H01L23/10 ,  H01L23/498 ,  H01L23/055 ,  H01L23/552 ,  H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

公开(公告)号：US11417630B2

公开(公告)日：2022-08-16

申请号：US16349543

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Digvijay A. Raorane ,  Ravindranath Vithal Mahajan ,  Mitul Bharat Modi

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498 ,  H01L23/367

Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.

公开(公告)号：US11322457B2

公开(公告)日：2022-05-03

申请号：US16849707

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane ,  Ian En Yoon Chin ,  Daniel N. Sobieski

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/50 ,  H01L23/498

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20210287975A1

公开(公告)日：2021-09-16

申请号：US16349583

申请日：2016-12-15

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane

IPC: H01L23/498 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a plurality of interconnects to couple a silicon interposer to a substrate; and a landing pad configured in a non-circle shape, wherein the plurality of interconnects are adjacent to the landing pad at one end of the plurality of interconnects through a plurality of vias.