公开(公告)号：US20150370567A1

公开(公告)日：2015-12-24

申请号：US14840014

申请日：2015-08-30

Applicant: Intel Corporation

Inventor： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

Abstract translation: 公开了用于本地指令集的虚拟化的方法，装置和系统。 实施例包括执行本地指令的处理器核心和第二核心，或者替代地，只有第二处理器核心在执行排除本地指令集的部分的第二指令集时消耗较少的功率。 第二核心解码器检测第二指令集的无效操作码。 微码层拆解器确定是否应翻译操作码。 翻译运行时环境识别包含第二指令集的无效操作码，其他无效操作码和中间有效操作码的可执行区域。 分析单元在执行无效操作码之前确定初始机器状态。 生成可执行区域的部分翻译，其中包括无效操作码的翻译和机器状态的状态恢复的封装，并将其保存到翻译高速缓冲存储器。

公开(公告)号：US11815979B2

公开(公告)日：2023-11-14

申请号：US16633120

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Yoni Aizik ,  Esfir Natanzon ,  Nir Rosenzweig ,  Nadav Shulman ,  Bart Plackle

IPC: G06F1/329 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F9/4893

Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：US11789516B2

公开(公告)日：2023-10-17

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/00 ,  G06F1/324

CPC classification number: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US20200174541A1

公开(公告)日：2020-06-04

申请号：US16206019

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Michael Bitan ,  Andrey Gabdulin ,  Efraim Rotem ,  Eli Efron ,  Nadav Shulman ,  David Ben Shimon ,  Nir Levitin ,  Esfir Natanzon

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/20

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

公开(公告)号：US10345889B2

公开(公告)日：2019-07-09

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/07

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20180120924A1

公开(公告)日：2018-05-03

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20170018051A1

公开(公告)日：2017-01-19

申请号：US15278316

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Esfir Natanzon ,  Ilya Osadchiy ,  Yoav Zach

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract translation: 可以使用一个处理器上的线程来使另一个处理器能够锁定或释放互斥体。 例如，图形处理单元可以使用中央处理单元线程来保护用于共享存储器的互斥体。

公开(公告)号：US20150377955A1

公开(公告)日：2015-12-31

申请号：US14319197

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Krishnakanth V. Sistla ,  Efraim Rotem ,  Eric Distefano ,  James G. Hermerding, II ,  Esfir Natanzon

IPC: G01R31/26 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3024 ,  G01R31/2856 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3058 ,  G06F11/3409 ,  G06F2201/81 ,  Y02D10/126 ,  Y02D10/172

Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

Abstract translation: 一种用户可配置可靠性控制回路的装置和方法。 例如，处理器的一个实施例包括：可靠性计量器，用于基于测量的处理器操作条件跟踪处理器的部件上的累积应力; 以及控制器，用于从用户或制造商接收压力限制信息，并且根据累积的应力和应力限制信息响应地在处理器上指定一组N个操作限制; 以及性能选择逻辑，用于基于由控制器指定的N个操作限制来输出处理器的一个或多个实际操作条件。

公开(公告)号：US20220179473A1

公开(公告)日：2022-06-09

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US11029744B2

公开(公告)日：2021-06-08

申请号：US15857802

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/20 ,  G06F11/30 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3206

Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.