公开(公告)号：US20240222238A1

公开(公告)日：2024-07-04

申请号：US18091543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.

公开(公告)号：US20240215269A1

公开(公告)日：2024-06-27

申请号：US18086232

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13023

Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.

公开(公告)号：US20240213116A1

公开(公告)日：2024-06-27

申请号：US18069507

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Dingying Xu ,  Xiaoying Guo ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/5383

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

公开(公告)号：US20240203806A1

公开(公告)日：2024-06-20

申请号：US18085291

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Bai Nie ,  Leonel R. Arana ,  Dingying XU ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Jeremy D. Ecton ,  Haobo Chen ,  Bin Mu

IPC: H01L23/15 ,  C03C17/00 ,  C03C17/06 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  C03C17/004 ,  C03C17/06 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  C03C2217/253 ,  C03C2218/365

Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

公开(公告)号：US20240194548A1

公开(公告)日：2024-06-13

申请号：US18065250

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Steve S. Cho ,  Hiroki Tanaka ,  Haobo Chen ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/15 ,  C23C18/16 ,  C23C18/18 ,  C23C18/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/15 ,  C23C18/1639 ,  C23C18/165 ,  C23C18/1855 ,  C23C18/48 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1011 ,  H01L2924/1511 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Apparatus and methods for electroless surface finishing on glass. A planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. Planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. The planar surface enables finishing the substrate surface with an electroless NiPdAu process.

公开(公告)号：US20250022786A1

公开(公告)日：2025-01-16

申请号：US18899851

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Haobo Chen ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Gamba ,  Bohan Shan ,  Robert May ,  Benjamin Taylor Duong ,  Bai Nie ,  Whitney Bryks

IPC: H01L23/498 ,  H01L23/08

Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.

公开(公告)号：US20240312865A1

公开(公告)日：2024-09-19

申请号：US18182879

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3733 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/15

Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.

公开(公告)号：US20240222257A1

公开(公告)日：2024-07-04

申请号：US18089801

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Rahul N. Manepalli ,  Brandon C. Marin ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/15

Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.

公开(公告)号：US20240222210A1

公开(公告)日：2024-07-04

申请号：US18091548

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.

公开(公告)号：US20240213170A1

公开(公告)日：2024-06-27

申请号：US18086293

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L23/49816 ,  H01L23/5386 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.