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    LOW-DEFECT GRAPHENE-BASED DEVICES & INTERCONNECTS
    12.
    发明申请
    LOW-DEFECT GRAPHENE-BASED DEVICES & INTERCONNECTS 审中-公开

    公开(公告)号：US20180350914A1

    公开(公告)日：2018-12-06

    申请号：US15777650

    申请日：2015-12-17

    Applicant: Intel Corporation

    Inventor： Paul A. ZIMMERMAN ,  Ian A. YOUNG ,  Wilman TSAI

    IPC: H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  C01B32/182

    CPC classification number: H01L29/1606 ,  C01B32/182 ,  H01L29/0665 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/778

    Abstract: Molecular Graphene (MG) of a physical size and bonding character that render the molecule suitable as a channel material in an electronic device, such as a tunnel field effect transistor (TFET). The molecular graphene may be a large polycyclic aromatic hydrocarbon (PAH) employed as a discrete element, or as a repeat unit, within an active or passive electronic device. In some embodiments, a functionalized PAH is disposed over a substrate surface and extending between a plurality of through-substrate vias. Heterogeneous surfaces on the substrate are employed to direct deposition of the functionalized PAH molecule to surface sites interstitial to the array of vias. Vias may be backfilled with conductive material as self-aligned source/drain contacts. Directed self-assembly techniques may be employed to form local interconnect lines coupled to the conductive via material. In some embodiments, graphene-based interconnects comprising a linear array of PAH molecules are formed over a substrate.

    TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS
    16.
    发明申请
    TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS 审中-公开
    隧道掘进围堰处理隧道场效应晶体管（TFETS）

    公开(公告)号：US20160056278A1

    公开(公告)日：2016-02-25

    申请号：US14779943

    申请日：2013-06-27

    Applicant: INTEL CORPORATION

    Inventor： Uygar E. AVCI ,  Raseong KIM ,  Ian A. YOUNG

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20

    CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66977 ,  H01L29/7391

    Abstract: Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions.

    Abstract translation: 描述了具有未掺杂漏极覆盖环绕区域的隧道场效应晶体管（TFET）。 例如，隧道场效应晶体管（TFET）包括形成在衬底上方的均质有源区。 同质结有源区包括掺杂源极区，未掺杂沟道区，缠绕区和掺杂漏极区。 在未掺杂的沟道区域，源极和缠绕区域之间形成栅电极和栅介质层。

    POLARIZATION GATE STACK SRAM
    17.
    发明申请
    POLARIZATION GATE STACK SRAM 有权

    公开(公告)号：US20210020233A1

    公开(公告)日：2021-01-21

    申请号：US17061272

    申请日：2020-10-01

    Applicant: Intel Corporation

    Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

    IPC: G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11

    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

    SEMICONDUCTOR DEVICE HAVING SUB REGIONS TO DEFINE THRESHOLD VOLTAGES
    20.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SUB REGIONS TO DEFINE THRESHOLD VOLTAGES 审中-公开

    公开(公告)号：US20190081044A1

    公开(公告)日：2019-03-14

    申请号：US16080974

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Uygar E. AVCI ,  Raseong KIM ,  Ian A. YOUNG

    IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/51 ,  H01L21/22 ,  H01L21/8238

    Abstract: Embodiments of the present disclosure describe a semiconductor device having sub regions or distances to define threshold voltages. A first semiconductor device includes a first gate stack having a first edge opposing a second edge and a first source region disposed on the semiconductor substrate. A second semiconductor device includes a second gate stack having a third edge opposing a fourth edge and a second source region disposed on the semiconductor substrate. A first distance extends from the first source region to the first edge of the first gate stack and a second distance different from the first distance extends from the second source region to the third edge of the second gate stack.

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