公开(公告)号：US20230238332A1

公开(公告)日：2023-07-27

申请号：US18128960

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/5381 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/13 ,  H01L23/53295 ,  H01L24/81 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/49822 ,  H01L21/4846 ,  H01L23/3128 ,  H01L21/486 ,  H01L23/5226 ,  H01L24/17 ,  H01L2224/81

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20220130742A1

公开(公告)日：2022-04-28

申请号：US17566523

申请日：2021-12-30

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20200381350A1

公开(公告)日：2020-12-03

申请号：US16636620

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US20200235053A1

公开(公告)日：2020-07-23

申请号：US16634864

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20180331036A1

公开(公告)日：2018-11-15

申请号：US15773950

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC: H01L23/528 ,  H01L23/66 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H01L23/00 ,  H01R13/6471

CPC classification number: H01L23/5286 ,  H01L21/4857 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/17 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R13/6471 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20240355745A1

公开(公告)日：2024-10-24

申请号：US18759008

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/075 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0753 ,  H01L25/167 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20220183177A1

公开(公告)日：2022-06-09

申请号：US17677785

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Gregorio R. MURTAGIAN ,  Kuang C. LIU ,  Kemal AYGUN

IPC: H05K7/10 ,  H05K1/11 ,  H05K1/02 ,  H01R13/24

Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

公开(公告)号：US20220093516A1

公开(公告)日：2022-03-24

申请号：US17540141

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20200343202A1

公开(公告)日：2020-10-29

申请号：US16393047

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Lijiang WANG ,  Jianyong XIE ,  Arghya SAIN ,  Xiaohong JIANG ,  Sujit SHARAN ,  Kemal AYGUN

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.