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    Method, apparatus and system to interconnect packaged integrated circuit dies
    11.
    发明授权
    Method, apparatus and system to interconnect packaged integrated circuit dies 有权

    公开(公告)号：US10396055B2

    公开(公告)日：2019-08-27

    申请号：US15749760

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/488 ,  H01L23/00 ,  H01L23/49 ,  H01L23/50 ,  H01L25/00 ,  H01L23/538

    Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

    Integrated circuit package having wirebonded multi-die stack
    12.
    发明授权
    Integrated circuit package having wirebonded multi-die stack 有权

    公开(公告)号：US10249598B2

    公开(公告)日：2019-04-02

    申请号：US15915769

    申请日：2018-03-08

    Applicant: INTEL CORPORATION

    Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

    IPC: H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

    Fan out packaging pop mechanical attach method
    13.
    发明授权
    Fan out packaging pop mechanical attach method 有权

    公开(公告)号：US12243856B2

    公开(公告)日：2025-03-04

    申请号：US18217000

    申请日：2023-06-30

    Applicant: Intel Corporation

    Inventor： David O'Sullivan ,  Georg Seidemann ,  Richard Patten ,  Bernd Waidhas

    IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

    INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
    14.
    发明申请
    INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK 有权

    公开(公告)号：US20230023328A1

    公开(公告)日：2023-01-26

    申请号：US17958298

    申请日：2022-09-30

    Applicant: INTEL CORPORATION

    Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

    IPC: H01L25/065 ,  H01L23/49 ,  H01L21/56 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

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