公开(公告)号：US20210103481A1

公开(公告)日：2021-04-08

申请号：US16969728

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Francesc Guim BERNAT ,  Karthik KUMAR ,  Susanne M. BALLE ,  Ignacio ASTILLEROS DIEZ ,  Timothy VERRALL ,  Ned M. SMITH

IPC: G06F9/50 ,  G06F9/48

Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.

公开(公告)号：US20240113954A1

公开(公告)日：2024-04-04

申请号：US18388461

申请日：2023-11-09

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Susanne M. BALLE ,  Rahul KHANNA ,  Sujoy SEN ,  Karthik KUMAR

IPC: H04L43/08 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06F15/16 ,  G06F16/901 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04B10/25 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14

CPC classification number: H04L43/08 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G06F1/183 ,  G06F1/20 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/30036 ,  G06F9/4401 ,  G06F9/544 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/1668 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F15/161 ,  G06F16/9014 ,  G08C17/02 ,  G11C5/02 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/3086 ,  H03M7/4056 ,  H03M7/4081 ,  H04B10/25891 ,  H04L41/145 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/0003 ,  H05K7/1442 ,  B25J15/0014

Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

公开(公告)号：US20220321491A1

公开(公告)日：2022-10-06

申请号：US17844506

申请日：2022-06-20

Applicant: Intel Corporation

Inventor： Susanne M. BALLE ,  Shihwei CHIEN ,  Duane E. GALBI ,  Nagabhushan CHITLUR

IPC: H04L47/43 ,  H04L67/133

Abstract: Examples described herein relate to a network interface device that includes circuitry to process data and circuitry to split a received flow of a mixture of control and data content and provide the control content to a control plane processor and provide the data content for access to the circuitry to process data, wherein the mixture of control and data content are received as part of a Remote Procedure Call. In some examples, provide the control content to a control plane processor, the circuitry is to remove data content from a received packet and include an indicator of a location of removed data content in the received packet.

公开(公告)号：US20220321434A1

公开(公告)日：2022-10-06

申请号：US17848898

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Andrzej KURIATA ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Susanne M. BALLE ,  Alexander BACHMUTSKY ,  Duane E. GALBI ,  Nagabhushan CHITLUR ,  Sundar NADATHUR

IPC: H04L43/04 ,  G06F9/54 ,  H04L67/133 ,  H04L43/0852 ,  H04L67/51

Abstract: Reliability and performance of a data center is increased by processing telemetry data in a network device in the data center. A Telemetry Correlation Engine (TCE) in the network device correlates host level telemetry received from a compute node with low-level network device telemetry collected in the network device to identify performance bottlenecks for microservices based applications. The Telemetry Correlation Engine processes and analyzes the telemetry data from the compute node and network statistics available in the network device.

公开(公告)号：US20210334138A1

公开(公告)日：2021-10-28

申请号：US17365898

申请日：2021-07-01

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Susanne M. BALLE ,  Slawomir PUTYRSKI ,  Rahul KHANNA ,  Paul DORMITZER

IPC: G06F9/48 ,  G06N5/02 ,  G06F9/50 ,  G06F30/34

Abstract: Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.

公开(公告)号：US20210073161A1

公开(公告)日：2021-03-11

申请号：US17088513

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Susanne M. BALLE ,  Evan CUSTODIO ,  Francesc GUIM BERNAT ,  Sujoy SEN ,  Slawomir PUTYRSKI ,  Paul DORMITZER ,  Joseph GRECCO

IPC: G06F13/40 ,  G06F13/36

Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.