公开(公告)号：US20220115323A1

公开(公告)日：2022-04-14

申请号：US17555219

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Thomas WAGNER ,  Adreas WOLTER ,  Bernd WAIDHAS

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L25/065 ,  H01L21/56

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

公开(公告)号：US20250112202A1

公开(公告)日：2025-04-03

申请号：US18374948

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Abdallah BACHA ,  Cindy MUIR ,  Mohan Prashanth JAVARE GOWDA ,  Stephan STOECKL ,  Thomas WAGNER ,  Wolfgang MOLZER

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/10 ,  H10B80/00

Abstract: Embodiments herein relate to systems, apparatuses, or processes for packages that include substrates that include one or more die in a cavity within the substrate, where sides and a bottom of the cavity are lined with a heat spreader, or TIM, material that is thermally coupled to a side of the substrate using thermally conductive vias. In embodiments, thermally conductive vias may be thermally coupled with the heat spreader at the side of the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240364000A1

公开(公告)日：2024-10-31

申请号：US18140361

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Thomas WAGNER ,  Georg SEIDEMANN ,  Harald GOSSNER ,  Telesphor KAMGAING ,  Shuhei YAMADA ,  Tae Young YANG

IPC: H01Q1/42 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/422 ,  H01Q1/2283 ,  H01Q9/0407

Abstract: Embodiments disclosed herein include a die module. In an embodiment, the die module comprises a die with a first surface and a second surface. In an embodiment, a first pad is on the second surface of the die, and a dielectric layer is over the second surface of the die and the first pad. In an embodiment, an antenna module is over the dielectric layer, where the antenna module comprises a second pad that is aligned over the first pad.

公开(公告)号：US20230103023A1

公开(公告)日：2023-03-30

申请号：US17448716

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Martin OSTERMAYR ,  Joachim SINGER ,  Klaus HEROLD

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor die is provided. The semiconductor die comprises a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure. A top surface of the electrically conductive structure is contacted at the front side of the semiconductor substrate and a bottom surface of the electrically conductive structure is contacted at a backside of the semiconductor substrate. Further, the semiconductor die comprises a backside metallization layer stack attached to the backside of the semiconductor substrate. A first portion of a wiring structure is formed in a first metallization layer of the backside metallization layer stack and a second portion of the wiring structure is formed in a second metallization layer of the backside metallization layer stack. Further, a tapered vertical connection is formed between the first portion of the wiring structure and the second portion of the wiring structure, wherein the first metallization layer is closer to the semiconductor substrate than the second metallization layer. A width of the tapered vertical connection increases towards the first metallization layer.

公开(公告)号：US20220336306A1

公开(公告)日：2022-10-20

申请号：US17855674

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Lizabeth KESER ,  Bernd WAIDHAS ,  Thomas ORT ,  Thomas WAGNER

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20220199562A1

公开(公告)日：2022-06-23

申请号：US17131663

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Thomas WAGNER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

公开(公告)号：US20250112191A1

公开(公告)日：2025-04-03

申请号：US18374920

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Pouya TALEBBEYDOKHTI ,  Stephan STOECKL ,  Lizabeth KESER

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package comprises an interposer with at least one open area through the interposer. A first die is connected to a first side of the interposer. A second die is connected to a second side of the interposer. At least one metal pillar is connected to the first die that extends through the open area of the interposer and connects to the second die to provide a direct die-to-die connection through the interposer.

公开(公告)号：US20240363567A1

公开(公告)日：2024-10-31

申请号：US18140465

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Thomas WAGNER ,  Georg SEIDEMANN ,  Harald GOSSNER ,  Telesphor KAMGAING ,  Shuhei YAMADA ,  Tae Young YANG

IPC: H01L23/00 ,  H01Q1/22 ,  H01Q1/38

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01Q1/2283 ,  H01Q1/38 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/05647 ,  H01L2224/08265 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32265 ,  H01L2924/0665

Abstract: Embodiments disclosed herein include a die module. In an embodiment, the die module comprises a die with a first surface and a second surface. In an embodiment, a first pad is on the second surface of the die, where a top surface of the first pad is substantially coplanar with the second surface. In an embodiment, the die module comprises an antenna module with a third surface and a fourth surface. In an embodiment, a second pad is on the third surface of the antenna module, where a bottom surface of the second pad is substantially coplanar with the third surface. In an embodiment, the top surface of the first pad directly contacts the bottom surface of the second pad.

公开(公告)号：US20240194552A1

公开(公告)日：2024-06-13

申请号：US18587331

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Lizabeth KESER ,  Bernd WAIDHAS ,  Thomas ORT ,  Thomas WAGNER

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L21/568 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/14 ,  H01L24/96 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02379 ,  H01L2924/19011

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20230197566A1

公开(公告)日：2023-06-22

申请号：US17644802

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Wolfgang MOLZER ,  Peter BAUMGARTNER ,  Thomas WAGNER ,  Joachim SINGER ,  Klaus HEROLD ,  Michael LANGENBUCH

IPC: H01L23/433 ,  H01L23/473 ,  H01L23/40 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L21/4871 ,  H01L23/473 ,  H01L23/4012 ,  H01L2023/4068

Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.