公开(公告)号：US10355384B2

公开(公告)日：2019-07-16

申请号：US15751018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Kit Chew Chee ,  Ahmad Jalaluddin Yusof ,  Tin Poay Chuah

IPC: H01R3/00 ,  H01R12/77 ,  H01R12/79 ,  H05K1/11 ,  H01R13/627 ,  H01R107/00 ,  H05K3/46

Abstract: In one example an electronic device comprises a chassis and a printed circuit board coupled to the chassis and comprising a body formed from a plurality of laminate layers, and at least one receptacle formed in the body and comprising at least one data connector positioned in the receptacle to provide a communication connection. Other examples may be described.

公开(公告)号：US20180233841A1

公开(公告)日：2018-08-16

申请号：US15751018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Kit Chew Chee ,  Ahmad Jalaluddin Yusof ,  Tin Poay Chuah

IPC: H01R12/77 ,  H01R12/79

CPC classification number: H01R12/774 ,  H01R12/79 ,  H01R13/6275 ,  H01R2107/00 ,  H05K1/117 ,  H05K1/118 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09163 ,  H05K2201/09481 ,  H05K2201/1034

Abstract: In one example an electronic device comprises a chassis and a printed circuit board coupled to the chassis and comprising a body formed from a plurality of laminate layers, and at least one receptacle formed in the body and comprising at least one data connector positioned in the receptacle to provide a communication connection. Other examples may be described.

公开(公告)号：US20180145016A1

公开(公告)日：2018-05-24

申请号：US15355961

申请日：2016-11-18

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Mooi Ling Chang ,  Eng Huat Goh ,  Say Thong Tony Tan ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5386

Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

公开(公告)号：US20250125242A1

公开(公告)日：2025-04-17

申请号：US18988169

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Santosh Gangal ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H10D1/47 ,  H10D1/68

Abstract: Disclosed herein are via plug resistors for incorporation into electronic substrates, and related methods and devices. Exemplary via plug resistor structures include a resistive element within and on a surface of a via extending at least partially through an electronic substrate and first and second electrodes coupled to the resistive element.

公开(公告)号：US12256487B2

公开(公告)日：2025-03-18

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Chin Lee Kuan ,  Tin Poay Chuah

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US12061502B2

公开(公告)日：2024-08-13

申请号：US17368851

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Tin Poay Chuah ,  Howe Yin Loo ,  Chin Kung Goh ,  Yew San Lim ,  Cora Shih Wei Nien

IPC: G06F1/20 ,  G06F1/16

CPC classification number: G06F1/203 ,  G06F1/1616

Abstract: According to the present disclosure, a laptop may be provided with a compartment including a moveable segment, an expandable heat exchanger with a movable section, and an expandable fan unit. The release of the movable segment of the compartment from a lower portion of the compartment produces an opening in the compartment and the movable section of the expandable heat exchanger is extended downward, and the expandable fan unit is lowered when the movable segment of the compartment is released.

公开(公告)号：US20230395480A1

公开(公告)日：2023-12-07

申请号：US17834674

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Jeff Ku ,  Min Suet Lim ,  Yew San Lim ,  Twan Sing Loo

IPC: H01L23/498 ,  H05K3/34 ,  H01L21/48 ,  H05K1/11

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K1/115 ,  H05K2201/10734 ,  H05K2201/0154 ,  H05K2201/10303 ,  H01L21/4853

Abstract: A substrate to printed circuit board (PCB) interconnect with liquid metal and surface pins. A thin dielectric sheet with drilled openings is adjacent to the bottom of a system on chip or CPU package substrate. Holes in the dielectric sheet have a liquid metal (LM) therein, the holes correspond to landing metal pads on the package substrate. The PCB includes surface pins in an arrangement to match the LM filled holes. A pick and place assembly of the package substrate to the PCB can be done without needing a reflow step. A magnet ring can be positioned on the polyimide sheet and configured to pair with a metal plate on the PCB. Guideposts around the periphery of the package substrate may be used to assist in alignment during assembly.

公开(公告)号：US11521943B2

公开(公告)日：2022-12-06

申请号：US17229316

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Chin Lee Kuan

IPC: H05K1/18 ,  H01L23/64 ,  H01L23/498 ,  H05K1/02 ,  H01L23/50 ,  H01L23/13

Abstract: A capacitor loop substrate assembly includes a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects are formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US11481001B2

公开(公告)日：2022-10-25

申请号：US17088620

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Chee Chun Yee ,  Tin Poay Chuah ,  Yew San Lim ,  Min Suet Lim ,  Jeff Ku

IPC: G06F1/16

Abstract: According to the various examples, a dual display system having a first panel having a first display area, a second panel having a second display area, and a connector assembly, attached to the first and second panels, that is configured to enable the first and second panels to rotate around three-directional axes. The connector assembly includes an elongated member and a hinge assembly, which are configured for attachment to the first and second display panels. The present dual display system may have several functional modalities, including use as a desktop computer, a laptop computer, a tablet, and a panoramic display.

公开(公告)号：US20220110214A1

公开(公告)日：2022-04-07

申请号：US17550746

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Martin M. Chang ,  Tin Poay Chuah ,  Eng Huat Goh ,  Chu Aun Lim ,  Min Suet Lim

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/30

Abstract: An apparatus comprising a package comprising a first side to interface with at least one chip; and a second side to interface with a circuit board, the second side opposite to the first side, wherein the second side comprises a non-stepped portion comprising a first plurality of conductive contacts; and a stepped portion that protrudes from the non-stepped portion, the stepped portion comprising a second plurality of conductive contacts.