公开(公告)号：US08711614B1

公开(公告)日：2014-04-29

申请号：US13052374

申请日：2011-03-21

申请人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

发明人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

IPC分类号： G11C11/34

CPC分类号： G11C8/10

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。 晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。 可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。 在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

公开(公告)号：US07920410B1

公开(公告)日：2011-04-05

申请号：US12391230

申请日：2009-02-23

申请人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

发明人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

IPC分类号： G11C11/00 ,  G11C5/06

CPC分类号： G11C8/10

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。 晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。 可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。 在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

公开(公告)号：US08921170B1

公开(公告)日：2014-12-30

申请号：US13408959

申请日：2012-02-29

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L21/338

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US08138797B1

公开(公告)日：2012-03-20

申请号：US12790660

申请日：2010-05-28

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US08995175B1

公开(公告)日：2015-03-31

申请号：US13350575

申请日：2012-01-13

申请人： Jun Liu ,  Irfan Rahim ,  Yanzhong Xu ,  Andy L. Lee

发明人： Jun Liu ,  Irfan Rahim ,  Yanzhong Xu ,  Andy L. Lee

IPC分类号： G11C11/412 ,  G11C5/14

CPC分类号： G11C5/14 ,  G11C11/412 ,  G11C11/418

摘要： A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.

摘要翻译： 描述了一种存储器电路，其包括存储器存储单元和耦合到存储器存储单元的存取晶体管，其中存取晶体管包括PMOS晶体管。 在一个实现中，存储器电路还包括耦合到存储器存储单元的偏置钳位晶体管。

公开(公告)号：US07800402B1

公开(公告)日：2010-09-21

申请号：US11982865

申请日：2007-11-05

申请人： Irfan Rahim ,  Sriram Muthukumar ,  William Bradley Vest ,  Myron Wai Wong

发明人： Irfan Rahim ,  Sriram Muthukumar ,  William Bradley Vest ,  Myron Wai Wong

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1778

摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.

摘要翻译： 可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。 数据信号可以通过互连路由到其他逻辑电路。 互连可以是可编程的。 可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。 连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。 可以提供电平移位电路以升高互连上的数据信号。 每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。 升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。

公开(公告)号：US20100148304A1

公开(公告)日：2010-06-17

申请号：US12332928

申请日：2008-12-11

申请人： Irfan Rahim ,  William Bradley Vest ,  Myron Wai Wong

发明人： Irfan Rahim ,  William Bradley Vest ,  Myron Wai Wong

IPC分类号： H01L29/00

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

摘要翻译： 为集成电路提供电源去耦电容。 去耦电容器可以在电源电路组件之间分布成簇。 每个集群可以包含并联连接的多个单独的电容器单元。 每个电容器单元可以包含与电容器串联的电容器和电阻器。 电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。 由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。

公开(公告)号：US09425192B2

公开(公告)日：2016-08-23

申请号：US12332928

申请日：2008-12-11

申请人： Irfan Rahim ,  William Bradley Vest ,  Myron Wai Wong

发明人： Irfan Rahim ,  William Bradley Vest ,  Myron Wai Wong

IPC分类号： H01L29/00 ,  H01L27/08 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

摘要翻译： 为集成电路提供电源去耦电容。 去耦电容器可以在电源电路组件之间分布成簇。 每个集群可以包含并联连接的多个单独的电容器单元。 每个电容器单元可以包含与电容器串联的电容器和电阻器。 电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。 由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。

公开(公告)号：US08502558B1

公开(公告)日：2013-08-06

申请号：US13281135

申请日：2011-10-25

申请人： Irfan Rahim ,  Andy L. Lee

发明人： Irfan Rahim ,  Andy L. Lee

IPC分类号： G06F7/38 ,  H23K19/173

CPC分类号： H03K19/17784

摘要： Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

摘要翻译： 集成电路提供有诸如多路复用器的电路，其可以被选择性地配置为将不同的可调电源电压路由到集成电路上的不同电路块。 电路块可以包含由电源电压供电的存储器元件，并且以由电源电压确定的量值提供对应的静态输出控制信号。 来自存储元件的控制信号可以被施加到电路块中的晶体管的栅极。 集成电路上的逻辑可以在给定的电源电压电平下供电。 存储元件可以以相对于给定电源电压电平升高的过驱动电压电平提供其输出信号。 与包含关键路径的电路块相关联的存储器元件可以在大于与包含非关键路径的电路块相关联的存储器元件的电压上被过载。

公开(公告)号：US08461869B1

公开(公告)日：2013-06-11

申请号：US13214147

申请日：2011-08-19

申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K19/17784

摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。