公开(公告)号：US07665416B2

公开(公告)日：2010-02-23

申请号：US11450871

申请日：2006-06-12

Applicant: Alexander Gschwandtner ,  Josef Mathuni ,  Alexander Mattheus ,  Stephan Schneider ,  Jürgen Sellmaier ,  Heinz Steinhardt

Inventor： Alexander Gschwandtner ,  Josef Mathuni ,  Alexander Mattheus ,  Stephan Schneider ,  Jürgen Sellmaier ,  Heinz Steinhardt

IPC: C23C16/00 ,  H01J7/24

CPC classification number: H01J37/32192 ,  H05H1/30

Abstract: An apparatus is described for generating excited and/or ionized particles in a plasma with a generator for generating an electromagnetic wave and an excitation chamber with a plasma zone in which the excited and/or ionized particles are formed. At least one excitation chamber is arranged in an insulating material off-center relative to a ring-cylindrical outer conductor.

Abstract translation: 描述了一种用于产生电磁波的发生器的等离子体中产生激发和/或离子化的颗粒的装置，以及具有形成激发和/或离子化的颗粒的等离子体区域的激发室。 至少一个激励室相对于环形圆柱形外部导体偏心地布置在绝缘材料中。

公开(公告)号：US06919147B2

公开(公告)日：2005-07-19

申请号：US10254405

申请日：2002-09-25

Applicant: Josef Mathuni ,  Gunther Ruhl

Inventor： Josef Mathuni ,  Gunther Ruhl

IPC: C03C17/34 ,  C03C17/36 ,  G03F1/00 ,  G03F1/32 ,  G03F1/80 ,  G03F1/08 ,  C23F1/00

CPC classification number: C03C17/3607 ,  C03C17/3435 ,  C03C17/36 ,  C03C17/3626 ,  C03C2218/33 ,  C03C2218/34 ,  G03F1/32 ,  G03F1/80

Abstract: The present invention provides a production method for a halftone phase mask which has an SiO2 substrate, an overlying refractory metal SixNy phase shifter layer (2) and an overlying chromium oxide or chromium mask layer (3), having the following steps: provision of a mask (4) on the chromium oxide or chromium mask layer (3); etching of the chromium oxide or chromium mask layer (3) for the purpose of forming a hard mask from the chromium oxide or chromium mask layer (3) in a first etching step; selective etching of the refractory metal SixNy phase shifter layer (2) using the hard mask in a plasma with a chlorine-containing and/or hydrogen-chloride-containing main gas in a second etching step with a predetermined cathode power of at least 20 W.

Abstract translation: 本发明提供了一种半色调相位掩模的制造方法，其具有SiO 2衬底，上覆难熔金属Si x N N y Y y移相器 层（2）和上覆的氧化铬或铬掩模层（3），具有以下步骤：在氧化铬或铬掩模层（3）上设置掩模（4）; 在第一蚀刻步骤中，为了从氧化铬或铬掩模层（3）形成硬掩模，蚀刻氧化铬或铬掩模层（3） 使用具有含氯和/或含氯化氢的等离子体中的硬掩模选择性蚀刻难熔金属Si x N y Y y移相层（2） 在第二蚀刻步骤中的主气体具有至少20W的预定阴极功率

公开(公告)号：US6013136A

公开(公告)日：2000-01-11

申请号：US764703

申请日：1996-12-02

Applicant: Josef Mathuni

Inventor： Josef Mathuni

IPC: H01L21/00 ,  H01L21/033 ,  H01L21/311 ,  C23C16/00

CPC classification number: H01J37/32192 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/67069

Abstract: A method for the manufacture of highly-integrated circuits on a semiconductor substrate includes applying coatings to front and back sides of a wafer of semiconductor material in at least one deposition process, and subsequently removing the coating on the back of the wafer by etching being carried out with the front of the wafer being free of lacquer. The etching is performed in a process chamber in which reactive particles produced in a plasma only reach the back of the wafer, while advances of the reactive particles toward the front of the wafer are prevented by a protective neutral gas.

Abstract translation: 一种用于在半导体衬底上制造高度集成电路的方法包括在至少一个沉积工艺中将涂层施加到半导体材料晶片的正面和背面，随后通过进行蚀刻而移除晶片背面的涂层 在晶片的前面没有漆。 在其中在等离子体中产生的反应性颗粒到达晶片背面的处理室中进行蚀刻，而通过保护性中性气体防止反应性颗粒朝向晶片前部的前进。

公开(公告)号：US5945351A

公开(公告)日：1999-08-31

申请号：US867115

申请日：1997-06-02

Applicant: Josef Mathuni

Inventor： Josef Mathuni

IPC: H01L21/302 ,  G03F7/16 ,  H01J37/32 ,  H01L21/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/683 ,  H01L29/30

CPC classification number: H01L21/02021 ,  H01J37/32357 ,  H01J37/32633 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/6708 ,  G03F7/168

Abstract: The apparatus and method of the invention allow etching of the edge of a semiconductor substrate even where no resist is applied to the front side and back side of the semiconductor substrate. The semiconductor substrate is introduced into a protective chamber within an evacuatable process chamber. The front side and the back side of the semiconductor substrate are covered by the protective chamber except for the edge of the semiconductor substrate to be etched. The edge of the semiconductor substrate is then exposed to an etching agent. Etching products and excess etching agent are removed.

Abstract translation: 本发明的装置和方法即使在半导体衬底的正面和背面没有抗蚀剂的情况下也可以蚀刻半导体衬底的边缘。 将半导体衬底引入可抽空处理室内的保护室中。 半导体衬底的前侧和后侧除了被蚀刻的半导体衬底的边缘之外被保护室覆盖。 然后将半导体衬底的边缘暴露于蚀刻剂。 去除蚀刻产物和多余的蚀刻剂。

公开(公告)号：US5489362A

公开(公告)日：1996-02-06

申请号：US211472

申请日：1994-08-29

Applicant: Heinz Steinhardt ,  Josef Mathuni

Inventor： Heinz Steinhardt ,  Josef Mathuni

IPC: E05D7/086 ,  A45C13/00 ,  B62D25/12 ,  E05D11/08 ,  E05F1/12 ,  E05F5/00 ,  F16C11/04 ,  F16F1/14 ,  H01J37/32 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/46 ,  H01L21/00

CPC classification number: H01J37/32357 ,  H01J37/32229 ,  E05Y2900/20

Abstract: A plasma discharge tube (5) having a diameter that corresponds to a quarter wavelength of the standing wave is selected and the waveguide system (2) is dimensioned and tuned such that the standing wave forms a first voltage maximum at a first side of the plasma discharge tube (5) and the standing wave is also supplied reflected, so that it forms a second, anti-phase voltage maximum at a second side of the plasma discharge tube (5) that lies opposite the first side and faces toward an end termination (12) of the waveguide system (2). A controlled magnetic field is applied in order to achieve an especially low working pressure.

Abstract translation: PCT No.PCT / EP92 / 02268 Sec。 371日期：1994年8月29日 102（e）日期1994年8月29日PCT提交1992年9月30日PCT公布。 公开号WO93 / 07639 日期为1993年4月15日。选择具有对应于驻波的四分之一波长的直径的等离子体放电管（5），并且对波导系统（2）进行尺寸调整，使得驻波形成第一电压最大值 在等离子体放电管（5）的第一侧，并且驻波也被反射，从而在等离子体放电管（5）的与第一相对的第二侧处形成第二反相电压最大值 并朝向波导系统（2）的端部终端（12）。 施加受控磁场以实现特别低的工作压力。

公开(公告)号：US5073515A

公开(公告)日：1991-12-17

申请号：US572262

申请日：1990-08-27

Applicant: Siegfried Roehl ,  Josef Mathuni

Inventor： Siegfried Roehl ,  Josef Mathuni

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10829

Abstract: Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned cooperating capacitor electrode. In a one-transistor memory cell having a trench capacitor in a semiconductor substrate (1), a field oxide (3) that isolates different cells is exploited for a self-aligning process. After the formation of a first electrode and of a dielectrode (5) of the capacitor, a conductive layer (6) is applied surface-wide, the upper edge thereof being higher over the field oxide (3) than over the field-oxide-free locations of the substrate (1). The raised location is exposed in a re-etching process upon employment of a planarizing auxiliary layer (9), and a sub-layer (10, 10') is selectively applied thereon, either by local oxidation, selective or non-selective deposition. This sub-layer (10, 10') serves as a self-aligned mask for the structuring of the conductive layer (6) as a cooperating electrode of the trench capacitor.

Abstract translation: 在具有自对准配合电容器电极的半导体衬底中制造单晶体管存储单元的沟槽电容器的方法。 在半导体衬底（1）中具有沟槽电容器的单晶体管存储单元中，利用隔离不同单元的场氧化物（3）进行自对准处理。 在电容器的第一电极和电介质（5）的形成之后，表面宽地施加导电层（6），其上边缘比场氧化物层（3）上面比场氧化物（3）高， 衬底（1）的自由位置。 在使用平面化辅助层（9）时，在再蚀刻工艺中暴露凸起位置，并且通过局部氧化，选择性或非选择性沉积选择性地在其上施加子层（10,10'）。 该子层（10,10'）用作用于构造作为沟槽电容器的配合电极的导电层（6）的自对准掩模。