公开(公告)号：US11875063B2

公开(公告)日：2024-01-16

申请号：US18082759

申请日：2022-12-16

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa ,  Tsukasa Tokutomi

IPC: G11C29/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C11/56 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C11/5621 ,  G11C11/5671 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

公开(公告)号：US11790986B2

公开(公告)日：2023-10-17

申请号：US17874926

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C11/00 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C16/30 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C2211/563 ,  G11C2211/5642 ,  H10B43/27 ,  H10B43/35

Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

公开(公告)号：US11756642B2

公开(公告)日：2023-09-12

申请号：US17476229

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kiwamu Watanabe ,  Kengo Kurose

IPC: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/06

CPC classification number: G11C29/12 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0673 ,  G11C16/08 ,  G11C16/26 ,  G11C2029/1202

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

公开(公告)号：US11537465B2

公开(公告)日：2022-12-27

申请号：US17174399

申请日：2021-02-12

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Masamichi Fujiwara ,  Kazumasa Yamamoto ,  Naoaki Kokubun ,  Tatsuro Hitomi ,  Hironori Uchikawa

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

公开(公告)号：US11915759B2

公开(公告)日：2024-02-27

申请号：US17556663

申请日：2021-12-20

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US11682464B2

公开(公告)日：2023-06-20

申请号：US17696339

申请日：2022-03-16

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G11C16/10

CPC classification number: G11C16/34 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/0483

Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

公开(公告)号：US11437096B2

公开(公告)日：2022-09-06

申请号：US17005443

申请日：2020-08-28

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C11/00 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  H01L27/11582 ,  G11C16/30 ,  H01L27/1157 ,  G11C16/08

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

公开(公告)号：US11238936B2

公开(公告)日：2022-02-01

申请号：US17014677

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US12283330B2

公开(公告)日：2025-04-22

申请号：US18354300

申请日：2023-07-18

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kiwamu Watanabe ,  Kengo Kurose

IPC: G11C29/12 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

公开(公告)号：US12165712B2

公开(公告)日：2024-12-10

申请号：US18362221

申请日：2023-07-31

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Shohei Asami ,  Masamichi Fujiwara

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.