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    Process-Induced Asymmetry Detection, Quantification, and Control Using Patterned Wafer Geometry Measurements
    12.
    发明申请
    Process-Induced Asymmetry Detection, Quantification, and Control Using Patterned Wafer Geometry Measurements 有权
    使用图案化晶圆几何测量的工艺诱导不对称检测，量化和控制

    公开(公告)号：US20160371423A1

    公开(公告)日：2016-12-22

    申请号：US14867226

    申请日：2015-09-28

    Applicant: KLA-Tencor Corporation

    Inventor： Pradeep Vukkadala ,  Jaydeep Sinha ,  Jong-Hoon Kim

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70633 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

    Abstract translation: 公开了使用图案化晶片几何测量来检测，量化和控制过程诱导的不对称签名的系统和方法。 该系统可以包括几何测量工具，其被配置成在晶片经历制造工艺之前获得晶片的第一组晶片几何测量，并且在制造工艺之后获得晶片的第二组晶片几何测量。 系统还可以包括与几何测量工具通信的处理器。 处理器可以被配置为：基于第一组晶片几何测量和第二组晶片几何测量来计算几何变化图; 分析几何变化图以通过制造过程检测诱导到晶片几何的不对称分量; 并且基于在晶片几何中检测到的不对称分量来估计由制造工艺引起的不对称重叠误差。

    Predicting and Controlling Critical Dimension Issues and Pattern Defectivity in Wafers Using Interferometry
    14.
    发明申请
    Predicting and Controlling Critical Dimension Issues and Pattern Defectivity in Wafers Using Interferometry 有权
    使用干涉测量法预测和控制晶片中的关键尺寸问题和图案缺陷

    公开(公告)号：US20160163033A1

    公开(公告)日：2016-06-09

    申请号：US14730997

    申请日：2015-06-04

    Applicant: KLA-Tencor Corporation

    Inventor： Pradeep Vukkadala ,  Sathish Veeraraghavan ,  Soham Dey ,  Jaydeep Sinha

    IPC: G06T7/00 ,  G06K9/62

    CPC classification number: G06T7/0004 ,  G06K9/6201 ,  G06T7/001 ,  G06T2207/10004 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

    Abstract: Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.

    Abstract translation: 公开了使用图案化晶片几何（PWG）测量在图案化晶片中预测和控制图案质量数据（例如临界尺寸和/或图案缺陷率）的系统和方法。 可以建立PWG测量和模式质量数据测量之间的相关性，并且可以利用所建立的相关性来基于为给定晶片获得的几何测量来为给定晶片提供图案质量数据预测。 可以将所产生的预测提供给光刻工具，光刻工具可以利用预测来校正可能在光刻工艺期间发生的焦点和/或标题误差。

    Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool
    18.
    发明授权
    Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool 有权
    使用晶圆尺寸几何工具的晶圆高阶形状表征和晶片分类的系统，方法和度量

    公开(公告)号：US09546862B2

    公开(公告)日：2017-01-17

    申请号：US13656143

    申请日：2012-10-19

    Applicant: KLA-Tencor Corporation

    Inventor： Haiguang Chen ,  Jaydeep Sinha ,  Sergey Kamensky ,  Sathish Veeraraghavan ,  Pradeep Vukkadala

    IPC: G01B11/24 ,  G06F17/00 ,  H01L21/66 ,  G01N21/95

    CPC classification number: G01B11/24 ,  G01B2210/56 ,  G01N21/9501 ,  G06F17/00 ,  H01L22/12

    Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

    Abstract translation: 公开了用于改善晶片高阶形状（HOS）表征和晶片分类的结果的系统和方法。 根据本公开的系统和方法基于局部形状。 将晶片图划分成多个测量点，以提高晶片形状表示的完整性。 可以针对晶片表征和/或分类目的计算各种基于站点的HOS度量值，并且还可以用作下游应用的控制输入。 此外，还提供了极坐标分割方案。 可以利用这种极性栅格划分方案将晶片表面划分成具有均匀位置区域的测量位置，同时提供良好的晶片边缘区域覆盖。

    Hybrid Phase Unwrapping Systems and Methods for Patterned Wafer Measurement
    19.
    发明申请
    Hybrid Phase Unwrapping Systems and Methods for Patterned Wafer Measurement 有权
    混合相位展开系统和图形晶片测量方法

    公开(公告)号：US20160321799A1

    公开(公告)日：2016-11-03

    申请号：US14808994

    申请日：2015-07-24

    Applicant: KLA-Tencor Corporation

    Inventor： Haiguang Chen ,  Jaydeep Sinha

    IPC: G06T7/00 ,  G01N21/95 ,  G01N21/88 ,  G01B11/24 ,  G01B11/06

    CPC classification number: G01N21/9501 ,  G01B11/06 ,  G01B11/2441 ,  G01N21/8851 ,  G01N2201/06113 ,  G01N2201/12 ,  G06T7/0004 ,  G06T2207/10056 ,  G06T2207/30148

    Abstract: Systems and methods for unwrapping phase signals obtained from interferometry measurements of patterned wafer surfaces are disclosed. A phase unwrapping method in accordance with the present disclosure may calculate a front surface phase map and a back surface phase map of a wafer, subtract the back surface phase map from the front surface phase map to obtain a phase difference map, unwrap the phase difference map to obtain a wafer thickness variation map, unwrap the back surface phase map to obtain a back surface map representing the back surface of the wafer; and add the wafer thickness variation map to the back surface phase map to calculate a front surface map representing the front surface of the wafer.

    Abstract translation: 公开了用于展开由图案化晶片表面的干涉测量获得的相位信号的系统和方法。 根据本公开的相位展开方法可以计算晶片的前表面相位图和背面相位图，从前表面相位图中减去背面相位图以获得相位差图，展开相位差 映射以获得晶片厚度变化图，展开背面相位图以获得表示晶片背面的背面图; 并将晶片厚度变化图添加到背面相位图以计算表示晶片前表面的前表面图。

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