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公开(公告)号：US07772689B2
公开(公告)日：2010-08-10
申请号：US11470432
申请日：2006-09-06
CPC分类号： H01L23/49827 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
摘要： It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to an upper surface 106b of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a lower surface 106a of the resin member 106.
摘要翻译： 其构造为包括半导体芯片110，用于形成其中安装该半导体芯片110的空腔109的树脂构件106和由图案布线105b构成的布线105，其形成为暴露于该树脂的上表面106b 构件106，并且还连接到半导体芯片110和其中一端连接到图案布线105b的后部105a，并且另一端形成为暴露于树脂构件106的下表面106a。
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公开(公告)号：US20080168652A1
公开(公告)日：2008-07-17
申请号：US12007040
申请日：2008-01-04
CPC分类号： H05K3/4614 , H05K3/462 , H05K3/4647 , H05K2203/061 , H05K2203/0733 , H05K2203/1327 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , Y10T29/4916 , Y10T29/49165
摘要： First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
摘要翻译： 首先，制造单层布线板，其具有在绝缘基材的两侧形成为所需形状的布线层; 以及在所述绝缘基体的一侧上的所述布线层上形成的金属凸块。 然后，准备并堆叠所需数量的单层板。 在这种情况下，准备设置在最上层的板，而不具有金属凸块。 这些板被定位和堆叠，使得相邻板中的一个的金属凸块连接到另一个板的对应的布线层。 此后，将树脂填充到堆叠板之间的间隙中，并且在通过上述步骤获得的多层板的两侧上形成绝缘层，以覆盖除了在布线上的预定位置限定的焊盘区域之外的整个表面 层。
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公开(公告)号：US20070052071A1
公开(公告)日：2007-03-08
申请号：US11470432
申请日：2006-09-06
IPC分类号： H01L23/495
CPC分类号： H01L23/49827 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
摘要： It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to a lower surface 106a of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a front surface 106b of the resin member 106.
摘要翻译： 其构造为包括半导体芯片110，用于形成其中安装该半导体芯片110的空腔109的树脂构件106和由图案布线105b构成的布线105，其形成为暴露于下表面106a 该树脂构件106还连接到半导体芯片110和其一端连接到图案布线105b的后部105a，并且另一端形成为暴露于前部表面106b 树脂构件106。
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公开(公告)号：US08468851B2
公开(公告)日：2013-06-25
申请号：US13600925
申请日：2012-08-31
申请人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
发明人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
IPC分类号： C03B5/225
CPC分类号： C03B5/2252 , Y02P40/57
摘要： A vacuum degassing apparatus for molten glass is comprised of an uprising pipe, a vacuum degassing vessel, a downfalling pipe, an upstream side pit that supplies molten glass to the uprising pipe, and a downstream side pit that receives molten glass from the downfalling pipe. The vacuum degassing apparatus for molten glass is further comprised of a separating mechanism that separates a part of molten glass moving from the downfalling pipe to the downstream side pit, and a returning pipe that returns separated molten glass to the upstream side pit.
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公开(公告)号：US08347654B2
公开(公告)日：2013-01-08
申请号：US12853408
申请日：2010-08-10
申请人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
发明人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
IPC分类号： C03B5/16
CPC分类号： C03B5/2252 , Y02P40/57
摘要： A vacuum degassing apparatus for molten glass is comprised of an uprising pipe, a vacuum degassing vessel, a downfalling pipe, an upstream side pit that supplies molten glass to the uprising pipe, and a downstream side pit that receives molten glass from the downfalling pipe. The vacuum degassing apparatus for molten glass is further comprised of a separating mechanism that separates a part of molten glass moving from the downfalling pipe to the downstream side pit, and a returning pipe that returns separated molten glass to the upstream side pit.
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公开(公告)号：US08096049B2
公开(公告)日：2012-01-17
申请号：US12929090
申请日：2010-12-30
IPC分类号： H01K3/00
CPC分类号： H05K3/4614 , H05K3/462 , H05K3/4647 , H05K2203/061 , H05K2203/0733 , H05K2203/1327 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , Y10T29/4916 , Y10T29/49165
摘要： First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
摘要翻译： 首先，制造单层布线板，其具有在绝缘基材的两侧形成为所需形状的布线层; 以及在所述绝缘基体的一侧上的所述布线层上形成的金属凸块。 然后，准备并堆叠所需数量的单层板。 在这种情况下，准备设置在最上层的板，而不具有金属凸块。 这些板被定位和堆叠，使得相邻板中的一个的金属凸块连接到另一个板的对应的布线层。 此后，将树脂填充到堆叠板之间的间隙中，并且在通过上述步骤获得的多层板的两侧上形成绝缘层，以覆盖除了在布线上的预定位置限定的焊盘区域之外的整个表面 层。
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公开(公告)号：US20070052083A1
公开(公告)日：2007-03-08
申请号：US11465284
申请日：2006-08-17
CPC分类号： H01L21/6835 , H01L21/4846 , H01L23/3107 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/105 , H01L2221/68345 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/01049
摘要： A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.
摘要翻译： 半导体封装100由半导体芯片110，用于密封该半导体芯片110的密封树脂106和形成在密封树脂106内部的布线105构成。 并且，布线105由连接到半导体芯片110的图案布线105b构成，并且还形成为暴露于密封树脂106的下表面106b，以及形成为在 密封树脂106的厚度方向，其一端连接到图案布线105b的另一端形成为暴露于密封树脂106的上表面106a。
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公开(公告)号：US20060022332A1
公开(公告)日：2006-02-02
申请号：US11188322
申请日：2005-07-25
申请人： Tetsuya Koyama , Tsuyoshi Kobayashi
发明人： Tetsuya Koyama , Tsuyoshi Kobayashi
IPC分类号： H01L23/34
CPC分类号： H01L24/82 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L2224/12105 , H01L2224/16225 , H01L2224/24226 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2224/92244 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H05K1/185 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip-embedded substrate comprising a supporting substrate and an insulating layer thereon, members for the connection to external circuits, and a plurality of semiconductor chips embedded in the insulating layer, wherein at least some of the plurality of semiconductor chips are embedded as a stack or stacks thereof. A method of manufacturing such a semiconductor chip-embedded substrate is also disclosed.
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公开(公告)号：US07955454B2
公开(公告)日：2011-06-07
申请号：US11516737
申请日：2006-09-07
CPC分类号： H05K3/4661 , H05K3/0035 , H05K3/108 , H05K3/381 , H05K2203/0554 , H05K2203/1152 , Y10T156/10 , Y10T156/1057 , Y10T156/1082
摘要： The method for forming wiring includes: laminating a thermosetting resin film and a metallic foil on an insulating substrate where base-layer wiring is formed, a mat surface of the metallic foil facing the resin film, pressing the film and the foil with application of heat; forming an opening in the metallic foil to expose a part of the insulating resin layer in which a via hole is to be formed; forming the via hole in the insulating resin layer by using as a mask the metallic foil; performing a desmear process of the via hole via the opening of the metallic foil; removing the metallic foil; forming an electroless-plated layer that covers the top surface of the insulating resin layer, a side surface of the via hole and a top surface of the base-layer wiring; and forming wiring including an electroplated layer on the electroless-plated layer.
摘要翻译： 形成布线的方法包括：在形成基底布线的绝缘基板上层叠热固性树脂膜和金属箔，金属箔的面向树脂膜的垫表面，施加热量来压制膜和箔 ; 在所述金属箔中形成开口以暴露要形成通孔的绝缘树脂层的一部分; 通过使用金属箔作为掩模在绝缘树脂层中形成通孔; 经由金属箔的开口进行通孔的去污处理; 去除金属箔; 形成覆盖绝缘树脂层的顶面，通孔的侧面和基底布线的顶面的无电镀层; 以及在所述化学镀层上形成包括电镀层的布线。
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公开(公告)号：US07882619B2
公开(公告)日：2011-02-08
申请号：US11818699
申请日：2007-06-14
IPC分类号： H02K15/085
CPC分类号： H02K15/068 , Y10T29/49009 , Y10T29/49073 , Y10T29/53143 , Y10T29/53157
摘要： Stator coils are inclined with respect to the axial direction of annularly arranged coil holding portions and such that at least parts of the stator coils overlap one another. In setting the stator coils on the coil holder, the stator coils are sequentially set on the coil holder in a predetermined direction, which is a coil setting direction, from the starting stator coil so as to overlap one another. The second section of the ending stator coil is set at the same position as a position where the first section of the starting stator coil is set in the circumferential direction or at a position advanced from the position where the first section of the starting stator coil is set in the circumferential direction. The ending stator coil is set on the coil holder to be further inward than the starting stator coil. Therefore, stator coils are evenly arranged.
摘要翻译： 定子线圈相对于环形布置的线圈保持部分的轴向倾斜，并且至少部分定子线圈彼此重叠。 在将定子线圈设置在线圈架上时，定子线圈从起动定子线圈沿预定方向（线圈设定方向）依次设置在线圈架上，以便彼此重叠。 终端定子线圈的第二部分设置在与起动定子线圈的第一部分在周向上或从起动定子线圈的第一部分的位置前进的位置处的位置相同的位置处 设置在圆周方向。 结束定子线圈设置在线圈架上比起动定子线圈更靠内侧。 因此，定子线圈均匀布置。
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