Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
    11.
    发明授权
    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
    具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法

    公开(公告)号:US07645645B2

    公开(公告)日:2010-01-12

    申请号:US11372334

    申请日:2006-03-09

    IPC分类号: H01L21/82

    摘要: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

    摘要翻译: 提出了用于集成电路的电可编程熔丝结构及其制造方法,其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处,并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向,而熔丝元件包括垂直于支撑表面定向的部分,并且包括至少一个直角弯曲部,其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。

    SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR
    13.
    发明申请
    SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
    半导体金属氧化物半导体场效应晶体管

    公开(公告)号:US20090212341A1

    公开(公告)日:2009-08-27

    申请号:US12034899

    申请日:2008-02-21

    IPC分类号: H01L29/788 H01L21/336

    摘要: An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.

    摘要翻译: 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料,并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层,内栅电极,外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管,或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

    Soi-body selective link method and apparatus
    15.
    发明授权
    Soi-body selective link method and apparatus 失效
    单体选择性联动方法及装置

    公开(公告)号:US06410369B1

    公开(公告)日:2002-06-25

    申请号:US09591511

    申请日:2000-06-12

    IPC分类号: H01L2100

    CPC分类号: H01L27/1104 H01L27/1203

    摘要: A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.

    摘要翻译: 绝缘体上硅(SOI)结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。 在硅层中形成至少两个至少两个SOI场效应晶体管(PFET)的p型体。 在硅层中还形成至少两个至少两个SOI场效应晶体管(NFET)的n型体。 最后,在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接,用于选择性地连接p型SOI FET或n型SOI FET的所需体,并允许连接体浮置。

    Selective reduction of sidewall slope on isolation edge
    16.
    发明授权
    Selective reduction of sidewall slope on isolation edge 失效
    隔离边缘侧壁倾斜的选择性减小

    公开(公告)号:US06228745B1

    公开(公告)日:2001-05-08

    申请号:US09460134

    申请日:1999-12-13

    IPC分类号: H01L2176

    CPC分类号: H01L21/76232 Y10S438/947

    摘要: Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.

    摘要翻译: 公开了一种半导体结构,其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。 晶体管还包括栅电极,栅极氧化物和有源区。 源极注入和漏极注入位于所述有源区的相对侧,并且所述栅极氧化物和栅电极位于所述有源区的顶部。 晶体管还包括与所述有源区相邻的两个沟槽隔离,其中所述沟槽隔离位于所述有源区的相对侧,使得每个沟槽的侧壁用作与所述有源区的界面,所述沟槽的至少一个侧壁 用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率,所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。

    DRAM cell having an annular signal transfer region
    18.
    发明授权
    DRAM cell having an annular signal transfer region 有权
    DRAM单元具有环形信号传送区域

    公开(公告)号:US06144054A

    公开(公告)日:2000-11-07

    申请号:US205934

    申请日:1998-12-04

    CPC分类号: H01L27/10864 H01L27/10841

    摘要: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

    摘要翻译: 一种存储器件,形成在具有形成在衬底中的侧壁的沟槽的衬底中。 该器件包括位线导体和字线导体。 信号存储节点具有形成在沟槽内的第一电极,第二电极和形成在第一和第二电极之间的节点电介质。 信号传递装置具有:(i)环形信号传递区域,其外表面邻近沟槽的侧壁,内表面,第一端和第二端; (ii)将信号传送区域的第一端耦合到第一扩散区域。 信号存储节点的第二电极; (iii)将信号传输区域的第二端耦合到位线导体的第二扩散区域; (iv)涂覆信号传送区域的内表面的栅极绝缘体; 和(v)涂覆栅极绝缘体并耦合到字线的栅极导体。 导电连接构件将信号传递区域耦合到参考电压以减少浮体效应。

    Large value capacitor for SOI
    20.
    发明授权
    Large value capacitor for SOI 失效
    SOI的大值电容器

    公开(公告)号:US5770875A

    公开(公告)日:1998-06-23

    申请号:US724287

    申请日:1996-09-16

    CPC分类号: H01L29/66181 H01L21/84

    摘要: Large capacitance, low-impedance decoupling capacitors in SOI and their method of fabrication. A high conductivity trench substrate contact is made adjacent to the capacitor by removal of insulator lining the capacitor by use of an extra mask thereby making a substrate contact when the trench is filled with doped polysilicon. The inventive process is compatible with and easily integrated into existing SOI logic technologies. The SOI decoupling capacitors are formed in trenches which pass through the silicon and buried oxide layers and into the underlying silicon substrate.

    摘要翻译: SOI中的大电容,低阻抗去耦电容及其制造方法。 通过使用额外的掩模去除夹在电容器上的绝缘体,使与电容器相邻的高导电性沟槽衬底接触,从而当沟槽填充有掺杂多晶硅时进行衬底接触。 本发明的方法与现有的SOI逻辑技术兼容并容易地集成。 SOI去耦电容器形成在通过硅和掩埋氧化物层并进入下面的硅衬底的沟槽中。