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公开(公告)号：US09349878B2
公开(公告)日：2016-05-24
申请号：US14313614
申请日：2014-06-24
Applicant: MACRONIX International Co., Ltd.
Inventor： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC: H01L29/792 , H01L29/788 , H01L27/115
CPC classification number: H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。
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公开(公告)号：US20140306282A1
公开(公告)日：2014-10-16
申请号：US14313614
申请日：2014-06-24
Applicant: MACRONIX International Co., Ltd.
Inventor： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC: H01L29/792
CPC classification number: H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。
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公开(公告)号：US11322207B1
公开(公告)日：2022-05-03
申请号：US17137461
申请日：2020-12-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Cheng-Hsien Cheng , Yu-Hung Huang , Chia-Hong Lee , Yin-Jen Chen
Abstract: A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.
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公开(公告)号：US10460797B2
公开(公告)日：2019-10-29
申请号：US15698812
申请日：2017-09-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shaw-Hung Ku , Ta-Wei Lin , Cheng-Hsien Cheng , Chih-Wei Lee , Wen-Jer Tsai
Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.
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公开(公告)号：US20170098478A1
公开(公告)日：2017-04-06
申请号：US14873486
申请日：2015-10-02
Applicant: Macronix International Co., Ltd.
Inventor： Chih-Wei Lee , Cheng-Hsien Cheng , Shaw-Hung Ku , Wen-Pin Lu
CPC classification number: G11C29/38 , G11C16/08 , G11C16/26 , G11C29/025 , G11C29/44 , G11C2029/1202
Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.
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Patent Agency Ranking
公开(公告)号：US09548121B2
公开(公告)日：2017-01-17
申请号：US14742944
申请日：2015-06-18
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chih-Wei Lee , Shaw-Hung Ku , Cheng-Hsien Cheng
IPC: G11C16/08 , G11C16/04 , H01L27/115 , H01L21/768
CPC classification number: G11C16/0483 , G11C2216/02 , H01L21/76802 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.
Abstract translation: 本文中设想的方法和装置用于增强非易失性存储器件的效率。 在示例实施例中，非易失性存储器件包括基板和非易失性存储单元的3D阵列，3D阵列包括通过绝缘层彼此分离的多个导电层，多个导电层包括顶层，顶部 层包括n个字符串选择行（SSL）和一个或多个底层，顶层还包括n-1个切割，每个切割电隔离两个SSL，其中每个切割被切割到顶层的深度并且不延伸到 底层和与多个层正交布置的多个垂直通道，多个通道中的每一个包括一串存储器单元，多个串中的每一个耦合到位线，SSL和一个或多个字线。
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公开(公告)号：US09437612B1
公开(公告)日：2016-09-06
申请号：US14832220
申请日：2015-08-21
Applicant: MACRONIX International Co., Ltd.
Inventor： Chih-Wei Lee , Cheng-Hsien Cheng , Shaw-Hung Ku , Wen-Pin Lu
IPC: H01L29/10 , H01L27/115 , H01L29/16 , H01L29/04 , H01L29/49 , H01L29/51 , H01L23/528 , H01L23/532 , H01L29/06
CPC classification number: H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L23/528 , H01L23/53271 , H01L27/11556 , H01L29/04 , H01L29/0649 , H01L29/16 , H01L29/4916 , H01L29/518 , H01L29/7889 , H01L29/7926
Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.
Abstract translation: 三维存储器，其包括存储单元堆叠结构。 存储单元堆叠结构由多个存储单元阵列结构和绝缘层交替堆叠，并且每个存储单元阵列结构包括字线，有源层，复合层和源极/漏极。 字线，有源层和复合层沿Y方向延伸。 有源层设置在相邻字线之间。 复合层设置在相邻字线和相邻有源层之间，并且每个复合层从有源层依次包括第一介电层，电荷存储层和第二介质层。 源/排水口以相等的间隔设置在活性层中。 存储单元包括两个相邻的源/漏极，两个相邻源极/漏极之间的有源层，有源层上的第一介电层，电荷存储层和第二介电层以及字线。
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公开(公告)号：US11361824B1
公开(公告)日：2022-06-14
申请号：US17164976
申请日：2021-02-02
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shaw-Hung Ku , Cheng-Hsien Cheng , Chun-Chang Lu , Wen-Jer Tsai
Abstract: Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.
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19.发明授权公开(公告)号：US10796753B1
公开(公告)日：2020-10-06
申请号：US16667653
申请日：2019-10-29
Applicant: MACRONIX International Co., Ltd.
Inventor： Yu-Hung Huang , Cheng-Hsien Cheng , Shaw-Hung Ku , Yin-Jen Chen
Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour. The shrinkage-quantity topographic contour and the program-shot-number topographic contour are overlapped to determine an operation region formed from an application range of the bit line voltage and an application range of the voltage difference value.
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公开(公告)号：US20190080750A1
公开(公告)日：2019-03-14
申请号：US15698812
申请日：2017-09-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shaw-Hung Ku , Ta-Wei Lin , Cheng-Hsien Cheng , Chih-Wei Lee , Wen-Jer Tsai
CPC classification number: G11C11/5628 , G11C16/3459 , G11C2211/5621
Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.
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