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    THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
    13.
    发明申请
    THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION 审中-公开

    公开(公告)号：US20170169885A1

    公开(公告)日：2017-06-15

    申请号：US15444982

    申请日：2017-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

    ERASABLE BLOCK SEGMENTATION FOR MEMORY
    14.
    发明申请
    ERASABLE BLOCK SEGMENTATION FOR MEMORY 有权
    可擦写存储区块

    公开(公告)号：US20160211022A1

    公开(公告)日：2016-07-21

    申请号：US15082664

    申请日：2016-03-28

    Applicant: Micron Technology, Inc.

    Inventor： Ramin Ghodsi

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G06F3/064 ,  G06F2212/00 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418

    Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

    Abstract translation: 各种实施例包括诸如那些具有被分成共享公共数据线的子块的存储器块的装置。 存储块的每个子块对应于多个分段源中的相应一个。 每个分段源与存储器块的其它分段源电隔离。 描述了附加的装置和操作方法。

    Applying substantially the same voltage differences across memory cells at different locations along an access line while programming
    15.
    发明授权
    Applying substantially the same voltage differences across memory cells at different locations along an access line while programming 有权
    在编程时沿着访问线在不同位置跨存储器单元施加大致相同的电压差

    公开(公告)号：US09349461B1

    公开(公告)日：2016-05-24

    申请号：US14558900

    申请日：2014-12-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Feng Pan ,  Ramin Ghodsi

    IPC: G11C11/34 ,  G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

    Abstract: An embodiment of a method of programming might include applying a first voltage difference across a first memory cell to be programmed, where applying the first voltage difference comprises applying a first channel bias voltage to a channel of the first memory cell, and applying a second voltage difference, substantially equal to the first voltage difference, across a second memory cell to be programmed while applying the first voltage difference across the first memory cell, where applying the second voltage difference comprises applying a second channel bias voltage to a channel of the second memory cell. The first channel bias voltage is different than the second channel bias voltage, and the first memory cell and the second memory cell are commonly coupled to an access line and are at different locations along a length of the access line.

    Abstract translation: 编程方法的一个实施例可以包括在待编程的第一存储器单元上施加第一电压差，其中施加第一电压差包括将第一通道偏置电压施加到第一存储器单元的通道，以及施加第二电压 在第一存储单元施加第一电压差的情况下跨越待编程的第二存储器单元实质上等于第一电压差的差值，其中施加第二电压差包括将第二通道偏置电压施加到第二存储器的通道 细胞。 第一通道偏置电压不同于第二通道偏置电压，并且第一存储器单元和第二存储单元通常耦合到接入线，并且沿着接入线的长度在不同的位置。

    Memory timing self-calibration
    16.
    发明授权
    Memory timing self-calibration 有权
    存储器定时自校准

    公开(公告)号：US09312022B1

    公开(公告)日：2016-04-12

    申请号：US14590344

    申请日：2015-01-06

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Ramin Ghodsi

    IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10 ,  G11C16/32 ,  G11C16/10 ,  G11C29/02 ,  G11C11/4093

    CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

    Abstract translation: 公开了用于存储器输入定时自校准的方法，用于输入定时自校准的装置和系统。 一种这样的方法包括将多个延迟微调设置顺序地编程到数据路径的延迟电路中。 数据路径可以包括耦合到延迟电路的数据锁存器。 时钟耦合到数据锁存器，将数据时钟数据插入数据锁存器。 数据的转换基本上与时钟的转换对齐。 在对每个延迟微调设置进行编程后，读取数据锁存器的输出。 在数据锁存器的第一输出状态和数据锁存器的第二输出状态之间确定边界，其中边界与多个延迟调整设置的特定延迟微调设置相关联。 特定的延迟调整设置被编程到延迟电路中。

    NAND FLASH MEMORY PROGRAMMING
    18.
    发明申请
    NAND FLASH MEMORY PROGRAMMING 有权
    NAND闪存编程

    公开(公告)号：US20140022847A1

    公开(公告)日：2014-01-23

    申请号：US14034266

    申请日：2013-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Ramin Ghodsi ,  Qiang Tang

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/12

    Abstract: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.

    Abstract translation: 一种对非易失性存储单元中的浮置栅极进行充电的方法包括：使存储单元内的衬底沟道达到第一电压，使控制栅极达到编程电压，并且在控制栅极处于编程电压的同时浮置衬底沟道电压 。 存储器件包括可操作以执行所述方法的状态机或控制器，并描述了这种状态机，存储器件和信息处理系统的操作。

    USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY
    19.
    发明申请
    USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY 有权
    使用闪存的非易失性存储器元件

    公开(公告)号：US20130242657A1

    公开(公告)日：2013-09-19

    申请号：US13889615

    申请日：2013-05-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ramin Ghodsi

    IPC: G11C16/04

    CPC classification number: G11C16/0408 ,  G11C11/005 ,  G11C13/0002 ,  G11C16/10 ,  G11C16/26

    Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.

    Abstract translation: 提供了操作存储器件的存储器件和方法，例如涉及利用新兴非易失性存储器（NV）元件代替典型的静态和/或动态组件的存储器架构的存储器件和方法。 新兴的NV存储器元件可以替代传统的锁存器，可以用作闪存阵列和外部设备之间的高速接口，并且还可以用作闪存阵列的高性能高速缓冲存储器。

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