公开(公告)号：US09773677B2

公开(公告)日：2017-09-26

申请号：US14820835

申请日：2015-08-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L21/225 ,  H01L29/167 ,  H01L29/04 ,  H01L29/06 ,  H01L21/265 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L27/108

CPC classification number: H01L21/2257 ,  H01L21/26513 ,  H01L23/528 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41741 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.

公开(公告)号：US09230968B2

公开(公告)日：2016-01-05

申请号：US14569337

申请日：2014-12-12

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi

IPC: H01L27/108 ,  H01L27/102 ,  H01L27/105 ,  H01L21/8222 ,  H01L21/8229 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L27/08 ,  H01L27/082 ,  H01L29/732 ,  H01L29/868

CPC classification number: H01L27/10876 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02598 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/8222 ,  H01L21/8229 ,  H01L21/823487 ,  H01L27/0814 ,  H01L27/0823 ,  H01L27/1021 ,  H01L27/1022 ,  H01L27/1052 ,  H01L27/1085 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/04 ,  H01L29/16 ,  H01L29/6609 ,  H01L29/66272 ,  H01L29/66666 ,  H01L29/732 ,  H01L29/868

Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.

公开(公告)号：US20150348785A1

公开(公告)日：2015-12-03

申请号：US14820835

申请日：2015-08-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L21/225 ,  H01L23/528 ,  H01L29/06 ,  H01L21/265 ,  H01L29/167 ,  H01L29/04

CPC classification number: H01L21/2257 ,  H01L21/26513 ,  H01L23/528 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41741 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.

Abstract translation: 形成半导体器件结构的掺杂元素的方法包括形成具有分隔衬底的茎部的底切部分的沟槽。 杆部分在衬底的基部和衬底材料的较宽部分之间延伸。 包括掺杂剂的载体材料至少在沟槽的底切部分中的茎的侧面上形成。 掺杂剂从载体材料扩散到茎中。 因此，衬底的窄茎部分掺杂有目标掺杂剂递送方法。 掺杂的茎可以形成或者结合在半导体器件结构的掩埋的，掺杂的导电元件中，诸如存储器阵列的数字线。 还公开了相关的半导体器件结构。

公开(公告)号：US20140315364A1

公开(公告)日：2014-10-23

申请号：US14319201

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US20140073100A1

公开(公告)日：2014-03-13

申请号：US14080417

申请日：2013-11-14

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US20140070306A1

公开(公告)日：2014-03-13

申请号：US14079821

申请日：2013-11-14

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/76232 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666

Abstract: Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods.

Abstract translation: 形成垂直存储器件的方法包括形成第一沟槽，至少部分地用多晶硅材料填充第一沟槽，以及形成大致垂直于第一沟槽的第二沟槽。 可以通过用第一材料去除作用去除硅和氧化物之一并且通过以不同的第二材料去除作用去除另一个硅和氧化物来形成第二沟槽。 形成装置的方法包括形成隔离沟槽，至少部分地用多晶硅材料填充隔离沟槽，以及形成大致垂直于隔离沟槽的字线沟槽，字线沟槽在字线端部区域中的深度约等于 或大于其在阵列区域中的深度。 字线可以形成在字线沟槽中。 半导体器件，垂直存储器件和器件通过这种方法形成。

公开(公告)号：US20240381646A1

公开(公告)日：2024-11-14

申请号：US18781329

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC: H10B43/27

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240363540A1

公开(公告)日：2024-10-31

申请号：US18768910

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53266 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240322049A1

公开(公告)日：2024-09-26

申请号：US18588352

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Haitao Liu ,  Michael A. Smith

IPC: H01L29/861 ,  H01L21/265 ,  H01L21/768 ,  H01L23/00 ,  H01L29/66 ,  H10B80/00

CPC classification number: H01L29/861 ,  H01L21/265 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/80 ,  H01L29/6609 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device including a first semiconductor device that includes a substrate, a memory array disposed above the substrate and below a frontside surface of the first semiconductor device, a plurality of source region contact (SRC) nodes disposed under the memory array, and a plurality of high-voltage (HV) diodes disposed in the substrate, each of the plurality of HV diodes being connected to corresponding one of the plurality of SRC nodes; and a second semiconductor device including a plurality of complementary-metal-oxide semiconductor (CMOS) devices, each of the plurality of CMOS devices being connected to, through a backside surface of the second semiconductor device and the frontside surface of the first semiconductor device, corresponding bond pad of the memory array, wherein fusion bonding exists between the backside surface of the second semiconductor device and the frontside surface of the first semiconductor device.

公开(公告)号：US12082416B2

公开(公告)日：2024-09-03

申请号：US17389864

申请日：2021-07-30

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.