公开(公告)号：US11501804B2

公开(公告)日：2022-11-15

申请号：US16992589

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn ,  Si-Woo Lee ,  Scott L. Light ,  Song Guo

IPC: H01L27/108 ,  G11C5/06

Abstract: A microelectronic device comprises a semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US09356096B2

公开(公告)日：2016-05-31

申请号：US14803662

申请日：2015-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Song Guo ,  Yushi Hu ,  Roy Meade ,  Sanh D. Tang ,  Michael P. Violette ,  David H. Wells

IPC: H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/32

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/04 ,  H01L29/32

Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.

公开(公告)号：US11925014B2

公开(公告)日：2024-03-05

申请号：US17643316

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: G11C11/24 ,  G11C11/408 ,  H10B12/00

CPC classification number: H10B12/312 ,  G11C11/4087 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US11877434B2

公开(公告)日：2024-01-16

申请号：US16924995

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H10B12/00 ,  H01L21/3065

CPC classification number: H10B12/053 ,  H01L21/3065 ,  H10B12/34

Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

公开(公告)号：US11201154B2

公开(公告)日：2021-12-14

申请号：US16729076

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: G11C11/24 ,  H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US10991700B2

公开(公告)日：2021-04-27

申请号：US16793888

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308 ,  G11C11/408

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US20200185389A1

公开(公告)日：2020-06-11

申请号：US16793888

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US10593678B1

公开(公告)日：2020-03-17

申请号：US16111499

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308 ,  G11C11/408

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US20250118353A1

公开(公告)日：2025-04-10

申请号：US18746473

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Song Guo ,  Yuan He ,  Kang-Yong Kim

IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4097

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US12022647B2

公开(公告)日：2024-06-25

申请号：US17323516

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Stephen D. Snyder ,  Thomas A. Figura ,  Siva Naga Sandeep Chalamalasetty ,  Ping Chieh Chiang ,  Scott L. Light ,  Yashvi Singh ,  Yan Li ,  Song Guo

IPC: H10B12/00 ,  G11C5/06 ,  H01L27/06

CPC classification number: H10B12/482 ,  G11C5/06 ,  H01L27/0688 ,  H10B12/30 ,  H10B12/488

Abstract: A microelectronic device comprises memory cell structures extending from a base material. At least one memory cell structure of the memory cell structures comprises a central portion in contact with a digit line, extending from the base material and comprising opposing arcuate surfaces, an end portion in contact with a storage node contact on a side of the central portion, and an additional end portion in contact with an additional storage node contact on an opposite side of the central portion. Related microelectronic devices, electronic systems, and methods are also described.