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    Circuit for voltage detection and protection and operating method thereof
    13.
    发明授权
    Circuit for voltage detection and protection and operating method thereof 有权
    电压检测和保护电路及其操作方法

    公开(公告)号：US09490624B2

    公开(公告)日：2016-11-08

    申请号：US14472520

    申请日：2014-08-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H02H3/20 ,  H02H3/24 ,  G11C5/14

    CPC classification number: H02H3/202 ,  G11C5/143 ,  H02H3/20 ,  H02H3/22 ,  H02H3/243 ,  H02H7/22

    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.

    Abstract translation: 用于电压检测和保护的电路包括第一块，第一电压检测器，第二块和第二电压检测器。 第一块接收第一个电压源。 第一电压检测器检测第一电压源，并且当检测到第一电压供应电平在第一工作电压范围之外时产生第一检测信号。 第二块接收第二电压源。 第二电压检测器检测第二电压源，并且当检测到第二电压供应电平在第二工作电压范围之外时产生第二检测信号。 当监视第一和第二检测信号中的至少一个时，第一块在电路上执行保护操作。

    Difference L2P method
    14.
    发明授权
    Difference L2P method 有权
    差异L2P法

    公开(公告)号：US09471485B2

    公开(公告)日：2016-10-18

    申请号：US13926633

    申请日：2013-06-25

    Applicant: Macronix International Co., Ltd.

    Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Han-Sung Chen

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

    Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.

    Abstract translation: 一种用于维护数据集的方法包括将数据集的基本副本存储在具有第一写入速度的第一非易失性存储器中，将具有第一非易失性存储器的第一变化数据集中的数据集的改变存储在具有第 第二写入速度，并通过读取基本副本和更改来生成数据集的当前副本。 如果达到第一改变数据集中的阈值数目，则将第一变化数据集的部分或全部移动到第一非易失性存储器中的第二变化数据集中，其中生成步骤包括读取第二变化 数据集。 如果达到第二改变数据集中的阈值数目，则通过读取基本副本和第一和第二非易失性存储器中的改变来生成当前副本。

    Plural operation of memory device
    16.
    发明授权
    Plural operation of memory device 有权
    存储设备的多种操作

    公开(公告)号：US09412460B2

    公开(公告)日：2016-08-09

    申请号：US14535042

    申请日：2014-11-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Tzung Shen Chen ,  Shuo Nan Hong ,  Yi Ching Liu ,  Chun-Hsiung Hung

    IPC: G11C11/34 ,  G11C16/26 ,  G11C16/12 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3422 ,  G11C16/3427 ,  G11C16/3431

    Abstract: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.

    Abstract translation: 集成电路器件包括半导体衬底，衬底上的第一存储器块，包括NAND存储器单元，在衬底上的第二存储器块，包括NAND存储器单元，以及控制器电路。 第一和第二存储器块可配置为响应于第一操作算法存储用于第一数据使用模式的数据以读取，编程和擦除数据，以及响应于第二操作算法读取数据使用的第二模式 ，分别编程和擦除数据。 控制器电路耦合到第一和第二存储器块，并且被配置为执行第一和第二操作算法，其中在第一操作算法中应用的读操作的字线通过电压处于比第二字的较低电压电平 用于在第二操作算法中应用的读操作的线通电压。

    Program verify with multiple sensing
    17.
    发明授权
    Program verify with multiple sensing 有权
    程序验证与多感测

    公开(公告)号：US09349469B2

    公开(公告)日：2016-05-24

    申请号：US14505297

    申请日：2014-10-02

    Applicant: Macronix International Co., Ltd.

    Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC: G11C16/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C16/3459

    Abstract: A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell.

    Abstract translation: 感测电路耦合到存储器阵列的位线。 耦合到感测电路的控制电路控制存储器单元的编程操作。 在编程存储器阵列中的存储单元的程序阶段之后，在程序验证阶段中，控制电路使得感测电路在程序验证阶段期间多次检测存储在存储器单元上的数据。 多次包括来自存储器单元的第一次感测数据和来自存储器单元的第二时间感测数据。

    PROGRAM VERIFY WITH MULTIPLE SENSING
    18.
    发明申请
    PROGRAM VERIFY WITH MULTIPLE SENSING 有权
    程序验证与多个感测

    公开(公告)号：US20160099069A1

    公开(公告)日：2016-04-07

    申请号：US14505297

    申请日：2014-10-02

    Applicant: Macronix International Co., Ltd.

    Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C16/3459

    Abstract: A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell.

    Abstract translation: 感测电路耦合到存储器阵列的位线。 耦合到感测电路的控制电路控制存储器单元的编程操作。 在编程存储器阵列中的存储单元的程序阶段之后，在程序验证阶段中，控制电路使得感测电路在程序验证阶段期间多次检测存储在存储器单元上的数据。 多次包括来自存储器单元的第一次感测数据和来自存储器单元的第二时间感测数据。

    Programming method, reading method and operating system for memory
    19.
    发明授权
    Programming method, reading method and operating system for memory 有权
    存储器的编程方法，读取方法和操作系统

    公开(公告)号：US09286158B2

    公开(公告)日：2016-03-15

    申请号：US14173873

    申请日：2014-02-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Chien-Hsin Liu ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/19 ,  H03M13/15

    CPC classification number: G06F11/1072 ,  G06F11/1012 ,  H03M13/1575 ,  H03M13/19

    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.

    Abstract translation: 提供了一种用于存储器的编程方法，读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码（ECC）。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据，使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。

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