利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.026 秒)

    Composite semiconductor device having function for overcurrent detection
    12.
    发明授权
    Composite semiconductor device having function for overcurrent detection 失效
    具有过电流检测功能的复合半导体器件

    公开(公告)号：US5023684A

    公开(公告)日：1991-06-11

    申请号：US575614

    申请日：1990-08-31

    申请人： Tetsujiro Tsunoda

    发明人： Tetsujiro Tsunoda

    IPC分类号： G01R15/20 ,  G01R19/165 ,  G01R31/26 ,  G01R31/30 ,  G01R33/00 ,  H01L43/02

    CPC分类号： G01R15/202 ,  G01R31/2644 ,  G01R31/3004 ,  H01L2224/48091 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091

    摘要： An insulating substrate has a U-shaped conductive layer which produces a magnetic field when a current flows therethrough as indicated by arrows. The substrate also includes a conductive layer on which a power semiconductor element is mounted through its main electrode. A current detector such as Hall effect elements is located inside the U-shaped conductive layer. When a load current flows through the semiconductor element, it flows through the conductive layer to produce the magnetic field since the other main electrode of the semiconductor element is electrically connected to one end of the conductive member through a metal wire. Accordingly, the load current flowing through the semiconductor element will be effectively detected by the current detector without connecting a resistor or current transformer to external terminals of a power semiconductor device, thereby providing a composite semiconductor device with a compact structure used for inverters for driving three-phase motors, etc.

    Insulated gate bipolar transistor having contact region with variable width
    13.
    发明授权
    Insulated gate bipolar transistor having contact region with variable width 有权
    具有可变宽度的接触区域的绝缘栅双极晶体管

    公开(公告)号：US08390097B2

    公开(公告)日：2013-03-05

    申请号：US11623932

    申请日：2007-01-17

    申请人： Takuya Hamaguchi ,  Hideki Haruguchi ,  Tetsujiro Tsunoda

    发明人： Takuya Hamaguchi ,  Hideki Haruguchi ,  Tetsujiro Tsunoda

    IPC分类号： H01L27/082

    CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

    摘要： An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.

    摘要翻译： IGBT包括排列成条的沟槽，形成为沿与沟槽交叉的方向延伸的第一发射极扩散层和形成为矩形形状的接触区域。 第一发射极扩散层上的接触区域的部分宽度比其他部分宽，宽度在与沟槽相交的方向上延伸。 这种配置允许发射极扩散层的发射极镇流电阻增加，导致由于短路而增强的电击穿耐性。

    POWER DEVICE
    14.
    发明申请
    POWER DEVICE 有权
    电源设备

    公开(公告)号：US20110133312A1

    公开(公告)日：2011-06-09

    申请号：US13058544

    申请日：2008-10-14

    申请人： Shigeo Tooi ,  Tetsujiro Tsunoda

    发明人： Shigeo Tooi ,  Tetsujiro Tsunoda

    IPC分类号： H01L29/739

    CPC分类号： H01L29/7395 ,  H01L29/0661 ,  H01L29/1095

    摘要： The present invention is a power device includes, a first conductive type semiconductor substrate, a second conductive type base region formed on a surface of the semiconductor substrate, a second conductive type collector region formed on a rear surface of the semiconductor substrate, a first conductive type emitter region formed on a surface of the base region, a trench gate formed via a gate insulating film in a first trench groove formed in the base region so as to penetrate the emitter region, a dent formed in the base region in proximity to the emitter region, a second conductive type contact layer formed on an inner wall of the dent, having a higher dopant density than that of the base region, a dummy trench formed via a dummy trench insulating film in a second trench groove formed at a bottom of the dent, and an emitter electrode electrically connected to the emitter region, the contact layer and the dummy trench, wherein the trench gate and the dummy trench reach the semiconductor substrate.

    摘要翻译： 本发明是一种功率器件，包括第一导电型半导体衬底，形成在半导体衬底的表面上的第二导电型基极区域，形成在半导体衬底的后表面上的第二导电类型集电极区域，第一导电类型 形成在基极区域的表面上的栅极型发射极区域，形成在基极区域中的第一沟槽中的栅极绝缘膜的沟槽栅极，以穿透发射极区域，形成在基极区域附近的凹陷 发射极区域，形成在凹陷内壁上的第二导电类型接触层，具有比基极区域更高的掺杂剂密度;在第二沟槽沟槽中形成的虚设沟槽，所述第二沟槽沟槽形成在底部 凹陷和电连接到发射极区域的发射极电极，接触层和虚设沟槽，其中沟槽栅极和虚拟沟槽到达半导体 ctor底物。

    Semiconductor device with enhanced switching speed and method for manufacturing the same
    15.
    发明授权
    Semiconductor device with enhanced switching speed and method for manufacturing the same 有权
    具有增强的开关速度的半导体器件及其制造方法

    公开(公告)号：US07777249B2

    公开(公告)日：2010-08-17

    申请号：US11753886

    申请日：2007-05-25

    申请人： Takuya Hamaguchi ,  Hideki Haruguchi ,  Tetsujiro Tsunoda

    发明人： Takuya Hamaguchi ,  Hideki Haruguchi ,  Tetsujiro Tsunoda

    IPC分类号： H01L29/74 ,  H01L29/43

    CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/32 ,  H01L29/66348

    摘要： A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.

    摘要翻译： 根据本发明的半导体器件的制造方法具有如下步骤：在晶片的第一主表面上形成具有第一导电类型的沟道的多个MOSFET; 将第一导电类型的杂质注入到晶片的第二主表面中的步骤，并且在条纹上进行激光退火处理，留出等距离的间隙，以形成已经被激活的缓冲层; 在形成缓冲层之后，将第二导电类型的杂质注入基板的第二主表面，并在第二主表面的整个表面上进行激光退火处理以形成集电体层并激活 缓冲层; 以及在所述第一主表面上形成发射极的步骤，以及在所述第二主表面上形成集电极。

    Manufacturing method of semiconductor device
    16.
    再颁专利
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：USRE41181E1

    公开(公告)日：2010-03-30

    申请号：US10817623

    申请日：2004-04-05

    申请人： Toru Takeda ,  Tetsujiro Tsunoda

    发明人： Toru Takeda ,  Tetsujiro Tsunoda

    IPC分类号： H01L21/425

    CPC分类号： H01L29/7802 ,  H01L21/261 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradiated by impurity ions, an excellent super junction is formed by controlling the ion acceleration energy and the width of each irradiated region so that the first and second conductivity-type regions may have a uniform impurity distribution and a uniform width along the direction of irradiation. Another method of manufacturing a low power dissipation semiconductor power device having an excellent super junction is provided which selectively irradiates a collimated neutron beam onto a P+ silicon ingot and forms an N+ region that has a uniform impurity distribution and a uniform width along the direction of irradiation in the P+ silicon ingot.

    摘要翻译： 提供了一种制造低功耗半导体功率器件的方法，其易于执行并且适于批量生产。 当在由杂质离子选择性照射的半导体衬底上形成第一和第二导电类型区域时，通过控制每个照射区域的离子加速能量和宽度来形成优异的超结，使得第一和第二导电型区域， 类型区域可以沿着照射方向具有均匀的杂质分布和均匀的宽度。 提供制造具有优异超结的低功耗半导体功率器件的另一种方法，其选择性地将准直的中子束照射到P +硅锭上，并形成沿着照射方向具有均匀杂质分布和均匀宽度的N +区 在P +硅锭中。

    INSULATED GATE SEMICONDUCTOR DEVICE
    17.
    发明申请
    INSULATED GATE SEMICONDUCTOR DEVICE 有权
    绝缘栅半导体器件

    公开(公告)号：US20080079066A1

    公开(公告)日：2008-04-03

    申请号：US11623932

    申请日：2007-01-17

    申请人： Takuya Hamaguchi ,  Hideki Haruguchi ,  Tetsujiro Tsunoda

    发明人： Takuya Hamaguchi ,  Hideki Haruguchi ,  Tetsujiro Tsunoda

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

    摘要： An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.

    摘要翻译： IGBT包括排列成条的沟槽，形成为沿与沟槽交叉的方向延伸的第一发射极扩散层和形成为矩形形状的接触区域。 第一发射极扩散层上的接触区域的部分宽度比其他部分宽，宽度在与沟槽相交的方向上延伸。 这种配置允许发射极扩散层的发射极镇流电阻增加，导致由于短路而增强的电击穿耐性。

    Semiconductor device
    18.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07091554B2

    公开(公告)日：2006-08-15

    申请号：US10740676

    申请日：2003-12-22

    申请人： Hiroki Muraoka ,  Hidetoshi Nakanishi ,  Tetsujiro Tsunoda ,  Shinichi Umekawa

    发明人： Hiroki Muraoka ,  Hidetoshi Nakanishi ,  Tetsujiro Tsunoda ,  Shinichi Umekawa

    IPC分类号： H01L29/76 ,  H01L23/62 ,  H01L29/94

    CPC分类号： H01L29/66348 ,  H01L29/0839 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7397 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device with high turn off capability includes a plurality of stripe trench lines which are provided in each of adjacent cell regions of a semiconductor layer in parallel and extended from one cell region toward the other cell region, a gate insulating film formed in each of the trench lines, and a gate electrode embedded in each of the trench lines with the gate insulating film interposed therebetween. In this semiconductor device, in each of the cell regions, part of adjacent ends of the plurality of trench lines on a side of the other cell region are connected to each other by connecting portions, and portions between the remaining adjacent ends are open. Moreover, at least one of the connecting portions of one cell region faces one of the open portions of the other cell region.

    摘要翻译： 具有高关断能力的半导体器件包括：多个条纹沟槽线，其设置在半导体层的相邻单元区域中并行并从一个单元区域朝向另一个单元区域延伸;栅绝缘膜， 沟槽线和嵌入每个沟槽线中的栅电极，其间插入栅极绝缘膜。 在该半导体装置中，在每个单元区域中，通过连接部分将多个沟槽线的另一个单元区域的一侧的相邻端部的一部分彼此连接，并且剩余的相邻端部之间的部分打开。 此外，一个单元区域的至少一个连接部分面向另一单元区域的开口部分之一。