公开(公告)号：US06515338B1

公开(公告)日：2003-02-04

申请号：US09533765

申请日：2000-03-23

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  Y10S257/90

摘要： A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一膜和第二膜，选择性地去除第二膜，第一膜和半导体衬底的顶部以形成第一槽，将第一绝缘体 在第一凹槽中形成隔离区域，对由隔离区域包围的第二膜进行构图以形成伪栅极层，使用伪栅极层作为掩模将杂质掺杂到半导体衬底上，在第二绝缘膜上形成第二绝缘膜 由虚拟栅极层和第一绝缘膜包围的半导体衬底，去除伪栅极层和第一膜以形成第二沟槽，在第二沟槽中的半导体衬底上形成栅极绝缘膜，并在栅极电极上形成栅电极 栅极绝缘膜在第二凹槽中。

公开(公告)号：US06313047B2

公开(公告)日：2001-11-06

申请号：US09811451

申请日：2001-03-20

申请人： Kazuhide Hasebe ,  Yuichiro Morozumi ,  Dong-Kyun Choi ,  Takuya Sugawara ,  Seiji Inumiya ,  Yoshitaka Tsunashima

发明人： Kazuhide Hasebe ,  Yuichiro Morozumi ,  Dong-Kyun Choi ,  Takuya Sugawara ,  Seiji Inumiya ,  Yoshitaka Tsunashima

IPC分类号： H01L2131

CPC分类号： H01L21/02183 ,  C23C16/0272 ,  C23C16/405 ,  H01L21/02271 ,  H01L21/31604

摘要： Disclosed is an MOCVD method of forming a tantalum oxide film. First, water vapor used as an oxidizing agent is supplied into a process container to cause moisture to be adsorbed on a surface of each semiconductor wafer. Then, PET gas used as a raw material gas is supplied into the process container and is caused to react with the moisture on the wafer at a process temperature of 200° C., thereby forming an interface layer of tantalum oxide. Then, PET gas and oxygen gas are supplied into the process container at the same time, and are caused to react with each other at a process temperature of 410° C., thereby forming a main layer of tantalum oxide on the interface layer.

摘要翻译： 公开了一种形成氧化钽膜的MOCVD方法。 首先，将作为氧化剂使用的水蒸气供给到处理容器中，使得水分吸附在各半导体晶片的表面上。 然后，将作为原料气体使用的PET气体供给到处理容器中，并在200℃的处理温度下与晶片上的水分反应，由此形成氧化钽界面层。 然后，将PET气体和氧气同时供给到处理容器中，并在410℃的处理温度下彼此反应，从而在界面层上形成氧化钽的主层。

公开(公告)号：US07968397B2

公开(公告)日：2011-06-28

申请号：US12659250

申请日：2010-03-02

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L21/38

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。

公开(公告)号：US20100065918A1

公开(公告)日：2010-03-18

申请号：US12561862

申请日：2009-09-17

申请人： Daisuke Ikeno ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

发明人： Daisuke Ikeno ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： A semiconductor device includes a semiconductor substrate containing a p-type diffusion layer and an n-type diffusion layer which are separated by an element separation film; a gate insulating film formed on or above the p-type diffusion layer and the n-type diffusion layer of the semiconductor substrate, respectively; a gate electrode containing a metallic film and formed on the gate insulating film; a Ge inclusion formed at an interface between the gate insulating film and the metallic film; and a silicon-containing layer formed on the metallic film.

摘要翻译： 半导体器件包括由元件分离膜分离的包含p型扩散层和n型扩散层的半导体衬底; 分别形成在所述p型扩散层和所述半导体衬底的n型扩散层上或之上的栅绝缘膜; 含有金属膜并形成在栅极绝缘膜上的栅电极; 形成在栅极绝缘膜和金属膜之间的界面处的Ge夹杂物; 以及形成在金属膜上的含硅层。

公开(公告)号：US20090194821A1

公开(公告)日：2009-08-06

申请号：US12359974

申请日：2009-01-26

申请人： Akio KANEKO ,  Seiji Inumiya ,  Tomonori Aoyama ,  Takuya Kobayashi

发明人： Akio KANEKO ,  Seiji Inumiya ,  Tomonori Aoyama ,  Takuya Kobayashi

IPC分类号： H01L29/68 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/823431 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

摘要： A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：在半导体衬底上形成SiGe晶体层，所述SiGe晶体层具有第一平面和相对于第一平面倾斜的第二平面; 在SiGe晶体层上形成非晶Si膜; 通过使用SiGe晶体层的第一和第二平面作为种子进行热处理，使位于非晶Si膜的第一和第二平面附近的部分结晶，从而形成Si晶体层; 通过热处理选择性去除或稀薄未结晶的非晶Si膜的一部分; 对Si晶体层的表面进行氧化处理，从而在Si晶体层的表面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极。

公开(公告)号：US07375403B2

公开(公告)日：2008-05-20

申请号：US10738049

申请日：2003-12-18

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物构成的栅极绝缘膜， 或四价金属氧化物和SiON的混合物，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且栅电极 由功能为4eV至5.5eV的金属制成。

公开(公告)号：US07368780B2

公开(公告)日：2008-05-06

申请号：US11763070

申请日：2007-06-14

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Hirokazu Ishida ,  Katsuaki Natori ,  Seiji Inumiya

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Hirokazu Ishida ,  Katsuaki Natori ,  Seiji Inumiya

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513

摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.

摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。

公开(公告)号：US20080054378A1

公开(公告)日：2008-03-06

申请号：US11889278

申请日：2007-08-10

申请人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

发明人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

IPC分类号： H01L29/76

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/78

摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

摘要翻译： 一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极 高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为 主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜 含有SiO 2作为主要成分的Hf，Zr和N.

公开(公告)号：US07141466B2

公开(公告)日：2006-11-28

申请号：US10962673

申请日：2004-10-13

申请人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

发明人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/518 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/78

摘要： According to the present invention, there is provided a semiconductor device comprising:an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer;a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film;a gate electrode formed on said gate insulating film; andsource and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：界面绝缘膜，其选择性地形成在半导体衬底的预定区域上，并且具有基本上一个原子层的膜厚度; 形成在所述界面绝缘膜上并具有高于所述界面绝缘膜的介电常数的介电常数的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及源极和漏极区，形成在位于所述栅电极下方的沟道区的两侧的所述半导体衬底的表面区域中。

公开(公告)号：US20060093731A1

公开(公告)日：2006-05-04

申请号：US11260253

申请日：2005-10-28

申请人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

IPC分类号： C23C16/52 ,  H05H1/24 ,  B05C11/00 ,  C23C16/00

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069 ,  H01L22/14

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.