公开(公告)号：US20210202501A1

公开(公告)日：2021-07-01

申请号：US16735098

申请日：2020-01-06

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Marc Aoulaiche ,  Albert Fayrushin

IPC: H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G06F3/06

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

公开(公告)号：US10937482B2

公开(公告)日：2021-03-02

申请号：US16432250

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Ankit Sharma ,  Haitao Liu ,  Albert Fayrushin ,  Akira Goda ,  Kamal M. Karda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/105

Abstract: A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.

公开(公告)号：US20190198673A1

公开(公告)日：2019-06-27

申请号：US15890530

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L29/78391 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/513 ,  H01L29/516

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

公开(公告)号：US12108601B2

公开(公告)日：2024-10-01

申请号：US17445867

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Marc Aoulaiche ,  Albert Fayrushin

IPC: H10B43/35 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  H10B43/27

CPC classification number: H10B43/35 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3427 ,  H10B43/27

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation and biasing the back gate while biasing the bit line and the word line.

公开(公告)号：US20230371264A1

公开(公告)日：2023-11-16

申请号：US17662982

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Kamal Karda ,  Gianpietro Carnevale ,  Aurelio Giancarlo Mauri

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.

公开(公告)号：US11742380B2

公开(公告)日：2023-08-29

申请号：US17714740

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Matthew J. King

IPC: G11C16/16 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/0638 ,  G11C16/0483 ,  G11C16/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

公开(公告)号：US20230031362A1

公开(公告)日：2023-02-02

申请号：US17387669

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/28

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

公开(公告)号：US20220293726A1

公开(公告)日：2022-09-15

申请号：US17714740

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Matthew J. King

IPC: H01L29/06 ,  G11C16/04 ,  H01L29/792 ,  H01L27/11529 ,  H01L29/423 ,  G11C16/16 ,  H01L27/11519 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/788 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

公开(公告)号：US11430809B2

公开(公告)日：2022-08-30

申请号：US16984457

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H01L27/11582 ,  G11C5/02 ,  H01L21/768 ,  G11C16/04 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220262820A1

公开(公告)日：2022-08-18

申请号：US17661659

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L29/06 ,  H01L21/762

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.