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公开(公告)号：US11868202B2
公开(公告)日：2024-01-09
申请号：US17946328
申请日：2022-09-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qisong Lin , Vamsi Pavan Rayaprolu , Jiangang Wu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Shao Chun Shi
CPC classification number: G06F11/0772 , G06F11/073 , G06F11/0751
Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.
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公开(公告)号：US20230317120A1
公开(公告)日：2023-10-05
申请号：US17426963
申请日：2020-12-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shuai Xu , Michele Piccardi , Arvind Muralidharan , June Lee , Qisong Lin , Scott A. Stoller , Jun Shen
IPC: G11C5/14
CPC classification number: G11C5/144
Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.
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公开(公告)号：US11710527B2
公开(公告)日：2023-07-25
申请号：US17868685
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Peter Feeley , Sampath K. Ratnam , Sivagnanam Parthasarathy , Qisong Lin , Shane Nowell , Mustafa N. Kaynak
CPC classification number: G11C16/34 , G06F3/0619 , G06F3/0634 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C29/00 , G11C29/84 , G11C16/0483 , G11C2207/229 , G11C2207/2272 , G11C2207/2281
Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
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公开(公告)号：US11704179B2
公开(公告)日：2023-07-18
申请号：US17452930
申请日：2021-10-29
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Harish R. Singidi , Ashutosh Malshe , Sampath K. Ratnam , Qisong Lin , Kishore Kumar Muchherla
CPC classification number: G06F11/076 , G06F3/064 , G06F3/0616 , G06F3/0646 , G06F3/0653 , G06F3/0679 , G06F11/0757 , G06F11/1068 , G06F11/3058
Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.
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公开(公告)号：US11693774B2
公开(公告)日：2023-07-04
申请号：US17412225
申请日：2021-08-25
Applicant: Micron Technology, inc.
Inventor： Jiangang Wu , Jing Sang Liu , Jung Sheng Hoei , Kishore Kumar Muchherla , Mark Ish , Myoung Jun Go , Nolan Tran , Qisong Lin
IPC: G06F12/00 , G06F12/0806
CPC classification number: G06F12/0806 , G06F2212/1024 , G06F2212/603
Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.
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Patent Agency Ranking
公开(公告)号：US20230073018A1
公开(公告)日：2023-03-09
申请号：US17986318
申请日：2022-11-14
Applicant: Micron Technology, Inc.
Inventor： Scott Anthony Stoller , Douglas Eugene Majerus , Qisong Lin
Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.
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公开(公告)号：US20230065231A1
公开(公告)日：2023-03-02
申请号：US17412225
申请日：2021-08-25
Applicant: Micron Technology, Inc.
Inventor： Jiangang Wu , Jing Sang Liu , Jung Sheng Hoei , Kishore Kumar Muchherla , Mark Ish , Myoung Jun Go , Nolan Tran , Qisong Lin
IPC: G06F12/0806
Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.
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公开(公告)号：US20220283952A1
公开(公告)日：2022-09-08
申请号：US17824676
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Abdelhakim Alhussien , Jiangang Wu , Karl D. Schuh , Qisong Lin , Jung Sheng Hoei
IPC: G06F12/0882 , G06F12/02 , G11C11/408 , G06F9/30 , G06F9/4401
Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.
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公开(公告)号：US11194646B2
公开(公告)日：2021-12-07
申请号：US16702399
申请日：2019-12-03
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Harish R. Singidi , Ashutosh Malshe , Sampath K. Ratnam , Qisong Lin , Kishore Kumar Muchherla
Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.
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公开(公告)号：US12001340B2
公开(公告)日：2024-06-04
申请号：US18124447
申请日：2023-03-21
Applicant: Micron Technology, Inc.
Inventor： Jiangang Wu , Qisong Lin , Jung Sheng Hoei , Yunqiu Wan , Ashutosh Malshe , Peng-Cheng Chen
IPC: G06F11/00 , G06F11/14 , G06F12/02 , G06F12/0811 , G06F12/0882 , G06F12/0891 , G06F13/16 , G11C16/06
CPC classification number: G06F12/0891 , G06F11/14 , G06F12/0246 , G06F12/0811 , G06F12/0882 , G06F13/1668 , G11C16/06
Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.
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