公开(公告)号：US20210202491A1

公开(公告)日：2021-07-01

申请号：US17203236

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20200105311A1

公开(公告)日：2020-04-02

申请号：US16702926

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Si-Woo Lee

IPC: G11C5/10 ,  H01L27/108 ,  G11C11/401

Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190259444A1

公开(公告)日：2019-08-22

申请号：US16234319

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4097

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US20250040130A1

公开(公告)日：2025-01-30

申请号：US18773001

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Kamal Karda ,  Haitao Liu ,  Scott E. Sills ,  Si-Woo Lee

IPC: H10B12/00

Abstract: Methods, systems, and devices for doping of memory cell selection transistors are described. Cell selection transistors of an array of memory cells may each include a semiconductor channel that is doped at a middle portion of the channel, which may support a deselection voltage for relatively high channel resistance that is relatively closer to or equal to a ground voltage than other transistor configurations. The semiconductor channels may include a p-type doping (e.g., using a configured concentration of boron) at a middle portion of the channels that is between end portions that are doped with an n-type doping (e.g., using phosphorous, arsenic, or a combination thereof, among other examples of n-type doping). In some implementations, undoped regions may be included between the n-type doped portions and the p-type doped portions. Such techniques may be implemented in horizontal cell selection transistors formed over a substrate, including for three-dimensional memory arrays.

公开(公告)号：US20240147693A1

公开(公告)日：2024-05-02

申请号：US18403970

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  H01L27/06

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688 ,  H10B12/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US20240064972A1

公开(公告)日：2024-02-22

申请号：US17892603

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Terrence B. Mcdaniel ,  Guangjun Yang ,  Vinay Nair

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10894

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes data lines; first structures located in a first region, electrically separated from each other, and including first conductive contacts coupled to the data lines; second conductive contacts located in the first region and coupled to memory elements of the apparatus; second structures located in a second region, electrically separated from each other, and including respective gates of transistors in the second region; a first dielectric material formed in the second region and including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and a second dielectric material formed over the first structures and the second structure. A portion of the second dielectric material contacts the first portion of the first dielectric material.

公开(公告)号：US11903183B2

公开(公告)日：2024-02-13

申请号：US17060457

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H01L27/108 ,  H10B12/00 ,  H01L27/06 ,  G11C5/02 ,  G11C5/10

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688 ,  H10B12/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US20240038588A1

公开(公告)日：2024-02-01

申请号：US17815359

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Vinay Nair ,  Russell A. Benson ,  Christopher W. Petz ,  Si-Woo Lee ,  Silvia Borsari ,  Ping Chieh Chiang ,  Luca Fumagalli

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. Conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.

公开(公告)号：US20230397390A1

公开(公告)日：2023-12-07

申请号：US17888460

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John F. Kaeding ,  Matthew S. Thorum ,  Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  Yoshitaka Nakamura ,  Glen H. Walters

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10873 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10805 ,  G11C5/063

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20220344338A1

公开(公告)日：2022-10-27

申请号：US17237664

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Litao Yang ,  Si-Woo Lee ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L27/108 ,  H01L27/11507 ,  H01L27/11514

Abstract: Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.