公开(公告)号：US20050006693A1

公开(公告)日：2005-01-13

申请号：US10617450

申请日：2003-07-11

申请人： Minh Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yang ,  Robert Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

发明人： Minh Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yang ,  Robert Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

IPC分类号： H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/115 ,  H01L29/511

摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

摘要翻译： 具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。 实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在 相同的沉积室。

公开(公告)号：US06642148B1

公开(公告)日：2003-11-04

申请号：US10126326

申请日：2002-04-19

申请人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

发明人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11568

摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

摘要翻译： 本发明一般涉及一种在半导体衬底内形成渐变结的方法。 在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。 半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。 第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。 然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

公开(公告)号：US06605517B1

公开(公告)日：2003-08-12

申请号：US10150282

申请日：2002-05-15

申请人： Jayendra D. Bhakta ,  Krishnashree Achuthan ,  Angela Hui

发明人： Jayendra D. Bhakta ,  Krishnashree Achuthan ,  Angela Hui

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/31053

摘要： A method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer. The method further includes performing an optimized polishing process on the oxide wherein the oxide is polished down to approximately a level of the nitride, but where more of the oxide is removed from the edge area of the wafer than in the center area. Thereafter, the nitride is stripped from the wafer, wherein substantially all of the nitride is removed from the wafer, thereby minimizing nitride residue.

摘要翻译： 一种用于在半导体制造期间从硅晶片减少氮化物残余物的方法。 晶片包括限定有源区域和隔离区域的氮化物掩模，其中隔离区域由沟槽形成。 该方法包括提供优化的氧化物沉积工艺，其中通过执行以下步骤来改善CVD室的温度梯度。 首先，将至少一个硅晶片放置在具有增加的槽尺寸，优选至少6mm的石英舟皿的室中。 第二，石英舟在大致中心的腔室中心，使得晶片位于腔室的中心部分，以避免腔室端部的温度梯度，使得当氧化物气体注入到晶片上时， 在晶片上形成厚度基本均匀的氧化物层。 该方法还包括对氧化物进行优化的抛光工艺，其中将氧化物抛光至氮化物的大致一定程度，但是从晶片的边缘区域除去氧化物中的比在中心区域更多的氧化物。 此后，从晶片剥离氮化物，其中基本上所有的氮化物从晶片中去除，从而使氮化物残留最小化。

公开(公告)号：US06465303B1

公开(公告)日：2002-10-15

申请号：US09885490

申请日：2001-06-20

申请人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

发明人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

摘要翻译： 本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底， 包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

公开(公告)号：US08445372B2

公开(公告)日：2013-05-21

申请号：US12644457

申请日：2009-12-22

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/285 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US08022468B1

公开(公告)日：2011-09-20

申请号：US11091519

申请日：2005-03-29

申请人： Minh Van Ngo ,  Wenmei Li ,  Jeffrey A. Shields ,  Ning Cheng ,  Angela Hui ,  Cinti Xiaohua Chen

发明人： Minh Van Ngo ,  Wenmei Li ,  Jeffrey A. Shields ,  Ning Cheng ,  Angela Hui ,  Cinti Xiaohua Chen

IPC分类号： H01L29/66

CPC分类号： H01L27/11521 ,  H01L23/552 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.

摘要翻译： 存储器件可以包括衬底，形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二介电层和形成在第二介电层上的控制栅极。 存储器件还可以包括在控制栅极和衬底上形成的层间电介质，其中层间电介质包括对紫外线辐射基本不透明的材料。

公开(公告)号：US20090111265A1

公开(公告)日：2009-04-30

申请号：US11924823

申请日：2007-10-26

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/4763

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US20090042378A1

公开(公告)日：2009-02-12

申请号：US11835538

申请日：2007-08-08

申请人： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  K.T. Chang ,  Huaqiang Wu

发明人： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  K.T. Chang ,  Huaqiang Wu

IPC分类号： H01L21/22

CPC分类号： H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。 与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

公开(公告)号：US20090039405A1

公开(公告)日：2009-02-12

申请号：US11835542

申请日：2007-08-08

申请人： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

发明人： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US20080265301A1

公开(公告)日：2008-10-30

申请号：US11796582

申请日：2007-04-26

申请人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillips Jones ,  Mark Chang ,  Minh-Van Ngo

发明人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillips Jones ,  Mark Chang ,  Minh-Van Ngo

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L21/28282 ,  H01L27/11568

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。 在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。 然后在核心单元之间完全或部分蚀刻捕获层。 去除非保形膜。 并形成顶部氧化物。 如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。