公开(公告)号：US11256894B2

公开(公告)日：2022-02-22

申请号：US16703616

申请日：2019-12-04

Applicant: QUALCOMM Incorporated

Inventor： Wesley James Holland ,  Rashmi Kulkarni ,  Ling Feng Huang ,  Huang Huang ,  Jeffrey Shabel ,  Chih-Chi Cheng ,  Satish Anand ,  Songhe Cai ,  Simon Peter William Booth ,  Bohuslav Rychlik

IPC: G06K9/00 ,  G06F21/32 ,  G01N21/31 ,  H04L9/32

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

公开(公告)号：US10339058B2

公开(公告)日：2019-07-02

申请号：US15658749

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Farrukh Hijaz ,  Bohuslav Rychlik

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0893 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1072 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0831

Abstract: Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.

公开(公告)号：US10338837B1

公开(公告)日：2019-07-02

申请号：US15946600

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Subrato Kumar De ,  Dexter Tamio Chun ,  Yanru Li ,  Bohuslav Rychlik ,  Richard Alan Stewart

IPC: G06F3/06 ,  G06N20/00

Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

公开(公告)号：US20190012204A1

公开(公告)日：2019-01-10

申请号：US15641469

申请日：2017-07-05

Applicant: QUALCOMM Incorporated

Inventor： Andrew TURNER ,  Bohuslav Rychlik ,  Zheng Liu

IPC: G06F9/50 ,  G06F9/48

Abstract: Various aspects include methods and computing devices implementing methods for reverse tiling of work items. Various aspects may include receiving information relating to a kernel execution, receiving information relating to a work item created for a kernel execution, and applying a reverse tiling function to produce a reverse tiling work item identifier (ID) for the work item to implement a pattern of access of the memory device resources. In various aspects, the reverse tiling function may be a static preprogrammed reverse tiling function, a a dynamically generated reverse tiling function, or a reverse tiling function selected from a plurality of reverse tiling functions. In various aspects, applying the reverse tiling function to produce the reverse tiling work item identifier for the work item may occur in response to determining that the pattern of access of a memory device resources provides a benefit over a default pattern of access.

公开(公告)号：US09792215B2

公开(公告)日：2017-10-17

申请号：US14672133

申请日：2015-03-28

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Meghal Varia ,  Serag Gadelrab

IPC: G06F12/12 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6028 ,  G06F2212/654 ,  G06F2212/684

Abstract: Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.

公开(公告)号：US09747213B2

公开(公告)日：2017-08-29

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/12 ,  G06F12/0846 ,  G06F12/1036 ,  G06F12/109

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

公开(公告)号：US09747209B1

公开(公告)日：2017-08-29

申请号：US15054295

申请日：2016-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Wang ,  Bohuslav Rychlik

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0868

CPC classification number: G06F12/0811 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/313

Abstract: Various embodiments of methods and systems for cache-level memory management in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through application of customized hashing algorithms at the lower level cache of individual application clients. Advantageously, for those application clients that do not require or benefit from hashing transaction traffic their transactions are not subjected to hashing. For those application clients that do benefit from hashing transaction traffic in order to minimize page conflicts at a double data rate (“DDR”) memory device, each client further benefits from a customized, and thus optimized, hashing algorithm. Because transaction streams arrive at the memory controller already hashed, or purposefully unhashed, the need for validating clients during a development phase is minimized.

公开(公告)号：US09626295B2

公开(公告)日：2017-04-18

申请号：US14807840

申请日：2015-07-23

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Bohuslav Rychlik

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0815 ,  G06F9/50

CPC classification number: G06F12/084 ,  G06F9/46 ,  G06F9/5088 ,  G06F12/0815 ,  G06F2212/314 ,  G06F2212/621

Abstract: Systems, methods, and computer programs are disclosed for scheduling tasks in a heterogeneous processor cluster architecture in a portable computing device. One embodiment is a system comprising a first processor cluster and a second processor cluster. The first processor cluster comprises a first shared cache, and the second processor cluster comprises a second shared cache. The system further comprises a controller in communication with the first and second processor clusters for performing task migration between the first and second processor clusters. The controller initiates execution of a task on a first processor in the first processor cluster. The controller monitors a processor workload for the first processor and a cache demand associated with the first shared cache while the task is running on the first processor in the first processor cluster. The controller migrates the task to the second processor cluster based on the processor workload and the cache demand.

公开(公告)号：US09442774B2

公开(公告)日：2016-09-13

申请号：US14195976

申请日：2014-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Sumit Sur ,  James M. Artmeier ,  Mark D. Guzzi ,  Philip T. Mueller, Jr. ,  Bohuslav Rychlik

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/50 ,  G06F1/20 ,  G06F1/32 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/329 ,  G06F1/3293 ,  G06F11/3058 ,  G06F11/3433 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/34

Abstract: Various embodiments of methods and systems for thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, and because more than one of the processing components may be capable of processing a given block of code, thermally aware workload scheduling techniques that compare performance curves of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by allocating workloads in real time, or near real time, to the processing components best positioned to efficiently process the block of code.

公开(公告)号：US09104411B2

公开(公告)日：2015-08-11

申请号：US13669043

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman Scott Gargash

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F9/50

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案，方案，系统和设备，配置为计算和实施性能保证，以确保处理器不处于忙碌状态（例如，由于临时工作负载）超过预定量 的时间高于该处理器完成其预先计算的稳态工作负载所需的时间。 DCVS可以基于可变延迟来调整处理器的频率和/或电压，以确保处理核心仅在最大程度上预定的最大工作量之下落在其稳态工作负载之后，而与工作频率或电压无关 的处理器。