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公开(公告)号：US20180329830A1
公开(公告)日：2018-11-15
申请号：US15592611
申请日：2017-05-11
Applicant: QUALCOMM Incorporated
Inventor： Richard Senior , Christopher Edward Koob , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
IPC: G06F12/1045 , G06F3/06
CPC classification number: G06F12/1036 , G06F3/06 , G06F3/0608 , G06F3/0661 , G06F3/0685 , G06F12/0238 , G06F12/0246 , G06F12/1009 , G06F12/1027 , G06F2212/1044 , G06F2212/401 , G06F2212/60
Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.
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公开(公告)号：US20140282508A1
公开(公告)日：2014-09-18
申请号：US13829023
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Erich James Plondke , Lucian Codrescu , Christopher Edward Koob , Piyush Patel , Thomas Andrew Sartorius
IPC: G06F9/455
CPC classification number: G06F9/45533 , G06F9/5016 , G06F12/109 , G06F2212/1021 , G06F2212/151 , G06F2212/656
Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。
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公开(公告)号：US20140208027A1
公开(公告)日：2014-07-24
申请号：US14219034
申请日：2014-03-19
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Ajay Anant Ingle , Lucian Codrescu , Jian Shen
IPC: G06F12/08
CPC classification number: G06F12/0895 , G06F12/0802 , G06F12/0864 , G06F17/505 , G06F2212/2515 , G06F2212/601
Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.
Abstract translation: 一种方法包括在高速缓存的标签状态阵列处接收地址，其中高速缓存可配置为具有小于第一大小的第一大小和第二大小。 所述方法还包括将所述地址的第一部分识别为设置索引，其中当所述高速缓冲存储器具有所述第一大小时，所述第一部分具有相同的位数，就像所述高速缓存具有所述第二大小一样。 所述方法还包括使用所述设置索引来定位所述标签状态阵列的至少一个标签字段，识别所述地址的第二部分以与存储在所述至少一个标签字段处的值进行比较，以定位所述标签状态阵列的至少一个状态字段 标签状态阵列，其与与第二部分匹配的特定标签字段相关联，基于当高速缓存具有该地址时，该地址的第三部分与至少一个状态字段的至少一个状态位的比较来识别高速缓存行 第二大小，并检索高速缓存行。
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公开(公告)号：US09785211B2
公开(公告)日：2017-10-10
申请号：US14622467
申请日：2015-02-13
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Xufeng Chen , Robert Allan Lester , Manojkumar Pyla , Peixin Zhong
CPC classification number: G06F1/26 , G06F1/3237 , G06F1/3287 , H03K19/0016 , Y02D10/128 , Y02D10/171
Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.
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公开(公告)号：US09658793B2
公开(公告)日：2017-05-23
申请号：US14627433
申请日：2015-02-20
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Erich James Plondke , Jiajin Tu
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F3/06 , G06F12/08 , G06F12/1027 , G06F1/32 , G06F9/30 , G06F12/0888
CPC classification number: G06F3/0634 , G06F1/32 , G06F3/0604 , G06F3/0673 , G06F9/30076 , G06F12/08 , G06F12/0888 , G06F12/1027 , G06F2212/1016 , G06F2212/1028 , G06F2212/502 , Y02D10/13
Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.
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Patent Agency Ranking
公开(公告)号：US10061698B2
公开(公告)日：2018-08-28
申请号：US15420667
申请日：2017-01-31
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Richard Senior , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
IPC: G06F12/08 , G06F12/0808 , G06F12/128
Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.
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公开(公告)号：US20180225224A1
公开(公告)日：2018-08-09
申请号：US15426473
申请日：2017-02-07
Applicant: QUALCOMM Incorporated
Inventor： Richard Senior , Christopher Edward Koob , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
IPC: G06F12/128 , G06F12/02
CPC classification number: G06F12/128 , G06F12/023 , G06F12/0875 , G06F12/0897 , G06F12/12 , G06F2212/1044 , G06F2212/401
Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.
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公开(公告)号：US20180173623A1
公开(公告)日：2018-06-21
申请号：US15385991
申请日：2016-12-21
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Richard Senior , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
IPC: G06F12/0804 , G06F12/12
CPC classification number: G06F12/0804 , G06F12/12 , G06F2212/1016 , G06F2212/1024 , G06F2212/1044 , G06F2212/401
Abstract: Aspects disclosed involve reducing or avoiding buffering evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operations. Metadata is included in cache entries in the uncompressed cache memory, which is used for mapping cache entries to physical addresses in the compressed memory system. When a cache entry is evicted, the compressed memory system uses the metadata associated with the evicted cache data to determine the physical address in the compressed system memory for storing the evicted cache data. In this manner, the compressed memory system does not have to incur the latency associated with reading the metadata for the evicted cache entry from another memory structure that may otherwise require buffering the evicted cache data until the metadata becomes available, to write the evicted cache data to the compressed system memory to avoid stalling write operations.
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公开(公告)号：US09678758B2
公开(公告)日：2017-06-13
申请号：US14499044
申请日：2014-09-26
Applicant: QUALCOMM Incorporated
Inventor： Lucian Codrescu , Christopher Edward Koob , Eric Wayne Mahurin , Suresh Kumar Venkumahanti
CPC classification number: G06F9/3877 , G06F9/30036 , G06F9/30043 , G06F9/3814 , G06F9/3824 , G06F9/3836 , G06F9/3887 , G06F15/8053
Abstract: Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.
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公开(公告)号：US08943293B2
公开(公告)日：2015-01-27
申请号：US14219034
申请日：2014-03-19
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Ajay Anant Ingle , Lucian Codrescu , Jian Shen
CPC classification number: G06F12/0895 , G06F12/0802 , G06F12/0864 , G06F17/505 , G06F2212/2515 , G06F2212/601
Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.
Abstract translation: 一种方法包括在高速缓存的标签状态阵列处接收地址，其中高速缓存可配置为具有小于第一大小的第一大小和第二大小。 所述方法还包括将所述地址的第一部分识别为设置索引，其中当所述高速缓冲存储器具有所述第一大小时，所述第一部分具有相同的位数，就像所述高速缓存具有所述第二大小一样。 所述方法还包括使用所述设置索引来定位所述标签状态阵列的至少一个标签字段，识别所述地址的第二部分以与存储在所述至少一个标签字段处的值进行比较，以定位所述标签状态阵列的至少一个状态字段 标签状态阵列，其与与第二部分匹配的特定标签字段相关联，基于当高速缓存具有该地址时，该地址的第三部分与至少一个状态字段的至少一个状态位的比较来识别高速缓存行 第二大小，并检索高速缓存行。
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